L. Fang, X. Wen, T. Fu, G. Wang, S. Miryala, T. Liu and P. Gui, “A 2.56 GS/s 12-bit 8x-Interleaved ADC with 156.6 dB FoMs in 65 nm CMOS", to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2021.

G. Wang, G. K. Sun, Q. Zhang, S. Elahmadi, and P. Gui, "A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC with Background Calibrated Fine and Coarse Comparators in 28 nm CMOS", in press, IEEE Transactions on VLSI (TVLSI), 10.1109/TVLSI.2019.2912887.

K. Sun, G. Wang, Q. Zhang, S. Elahmadi, and P. Gui, "A 56 GS/s 8 bit time-interleaved ADC with ENOB and BW enhancement techniques in 28 nm CMOS”, Accepted for publication in IEEE Journal of Solid-State Circuits (JSSC).

K. Sun, G. Wang, Q. Zhang, S. Elahmadi, and P. Gui, "A 31.5-GHz BW 6.4-b ENOB 56-GS/s ADC in 28nm CMOS for 224-Gb/s DP-16QAM Coherent Receivers”, Proceedings of IEEE Custom Integrated Circuits Conference (CICC), San Diego, 2018.

G. Wang, K. Sun, Q. Zhang, S. Elahmadi, and P. Gui, "A 43.6-dB SNDR 1-GS/s Single-Channel SAR ADC using Coarse and Fine Comparators with Background Comparator Offset Calibration”, Proceedings of IEEE European Solid-State Circuits Conference (ESSCIRC), Leuven, Belgium, 2017.

Z. Zeng, G. Wang, K. Sun, S. Kulis, P. Moreira, and P. Gui, “A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology”, IEEE Transactions on Nuclear Science, Vol. 64, Iss. 4, 2017.

Z. Zeng, T. Zhang, G. Wang, P. Gui, S. Kulis and P. Moreira, "LDQ10: A Compact Ultra Low-Power Radiation-Hard 4X10 Gb/s Driver array," accepted to Journal of Instrumentation 12 P02020, January 2017, doi: 10.1088/1748-0221/12/02/P02020.

G. Wang, F. Kacani, and Y. Chiu, “IRD Digital Background Calibration of SAR ADC with Coarse Reference ADC Acceleration,” IEEE Transactions on Circuits and Systems II, Vol. 61, no. 1, pp. 11-15, Jan. 2014.

G. Wang, Y. Chiu, “Fast FPGA Emulation of Background-Calibrated SAR ADC with Internal Redundancy Dithering,” IEEE Custom Integrated Circuits Conference, CICC’13, San Jose, CA, 2013.