EE 2181 Digital Computer Logic - Spring 2007

Analysis and synthesis of combinational and sequential digital circuits. Basic digital computer logic circuits are designed, simulated using Verilog HDL and implemented using a Digi-Designer kit and integrated circuits. Concurrent registration in EE 2381.

  Yasser Ghanbari - Lab TA

Office Location: Junkins Building 320
Office Phone: 214-768-3783
Email Address: yghanbari@smu.edu
Office Hours: Tu 11:00 - 11:50 am
  Tu 4:00 - 4:50 pm
  W 1:00 - 1:50 pm
  By Appointment

Course Handouts [PDF format]

Course Syllabus Karnaugh Maps - 3 Karnaugh Maps - 4 TTL Pinouts
Verilog Tutorial Running Verilog: Terminal Running Verilog: Interactive Verilog & FSM

Labs

  1. Laboratory Orientation
  2. Digital Logic - Gates
  3. Digital Logic - Circuits
  4. Digital Logic - Delays
  5. Combinational Logic Design
  6. Multiplexers and Demultiplexers - Part I
  7. Multiplexers and Demultiplexers - Part II
  8. Dataflow Modeling and UDPs
  9. Set-Reset Latch
  10. Counter Design Using J-K Flip-Flops
  11. Master-Slave J-K Flip-Flop
  12. Sequential Network Design
  13. Shift Registers

Links to Electronic Devices and Datasheets

  1. CMP Media - Chip Select
  2. Logic Families - Texas Instruments, Inc.
  3. Logic Reference Guide - Texas Insturments, Inc.
  4. IEEE Standard Symbols - Digital Design Principles and Practices by John F. Wakerly, Textbook Web Site.
  5. Timely Electrical & Logic Symbol Templates

Lab Equipment [PDF format]

Digi Designer Box HP E3631A Power Supply HP E3478A Digital Multimeter HP 54624A Oscilloscope

Texas Instruments, Inc. TTL Data Sheets <http://focus.ti.com> [PDF format]

74LS00 Quad 2-Input NAND 74LS02 Quad 2-Input NOR 74LS04 Hex Inverters
74LS08 Quad 2-Input AND 74LS11 Triple 3-Input AND 74LS27 Triple 3-Input NOR
74LS32 Quad 2-Input OR 74LS74A Dual D FF with Preset and Clear 74LS107A Dual J-K FF with Clear
74LS112A Dual J-K FF with Preset and Clear 74LS160 Synchronous 4-Bit Counters 74LS164 8-Bit Parallel-Out Serial Shift Register
74ALS166 Parallel-Load 8-Bit Shift Register 74ALS169B Synchronous 4-Bit Up/Down Binary Counters 74LS194A Bidirectional Universal Shift Registers

Fairchild Semiconductor. CD4000BC Data Sheets <http://www.fairchildsemi.com> [PDF format]

CD4011BC Quad 2-Input NAND Gate CD4001BC Quad 2-Input NOR Gate CD4069UBC Hex Inverters
CD4081BC Quad 2-Input AND Gate CD4071BC Quad 2-Input OR Gate CD4013BC Dual D FF with Clear

Course Downloads [Zip format]

Lab 02 - Figure 01   Lab 04 - Figure 02    

Verilog Downloads [Zip format]

Verilog Tutorial Examples Binary Adders D-Latch Dataflow Modeling and UDPs
Flip-Flop Models Counter Design Flip-Flop Timing Diagram Moore & Mealy
FSM Example #1 FSM Example #2 False Output Verilog & FSMs
Basic Shift Register