A synthesized Verilog file (produced by an RTL compiler) can be placed and routed. Placement arranges the standard cells of the design into rows on a chip, while routing determines how to wire the interconnections (nets) of the design. The Cadence Innovus Place & Route tool is available on the Lyle machines. Set up X-Windows access as you did for the Synopsys Design Compiler to run Innovus.