RTL Compiler - Synopsys Design Compiler
After you have simulated and verified that your Verilog code is
working properly, you can compile the Verilog modules to produce a
circuit that is optimized for various criteria (area, timing, power).
The Synopsys Design Compiler (SDC) is available on the Lyle machines.
Set up X-Windows access as you did for the Cadence Verilog tool to run
SDC.
A useful tutorial to get started is the following:
The tutorial describes certain files that you will need - these files are:
Tool Tips
To save an image of the current window or active view
- Choose View > Save Screenshot As. The Save Screenshot As dialog
box appears.
- Select the file, or enter the path and file name in the "File
name" box. The default format is PNG. You can specify a different
format by using its extension to the file name.
- To save an image of the active view window instead of the
top-level GUI window in which you are working, select the "Grab
screenshot of active view only" option.
- Click Save.
T. Manikas
Last update 2020 Dec 9