Theodore W. Manikas
CV
Version 7/20/2023
Associate Chair, Department of Computer Science, Southern Methodist University, 2023 – present.
Clinical Professor, Department of Computer Science, Southern Methodist University, 2019 – present.
Clinical Professor, Department of Computer Science and Engineering, Southern Methodist University, 2015 – 2018.
Lecturer, Department of Computer Science and Engineering, Southern Methodist University, 2012 – 2015.
Research Associate Professor, Department of Computer Science and Engineering, Southern Methodist University, 2010 - 2012.
Visiting Research Professor, Department of Computer Science and Engineering, Southern Methodist University, 2009 – 2010.
Co-Director, Institute of Nanotechnology, University of
Tulsa, 2007 - 2009.
Assistant
Professor, Department of Electrical
Engineering, University of Tulsa, 2000 - 2009.
Computer engineering, genetic algorithms, and computer-aided design methods. Application areas include computer security, VLSI circuit design and testing.
Licensed Professional Engineer, Texas, Oklahoma
1. M. Thornton, E. Larson, T. Manikas, M. Taylor, A. Sinha, N. Srirama (2023). “Control System Anomaly Detection using Neural Network Consensus”. U.S. Patent No. US-11546205-B1. Washington, DC: U.S. Patent and Trademark Office.
Ph.D., Electrical Engineering (with minors in Computer Science and Statistics), University of Pittsburgh
M.S.,
Electrical Engineering,
B.S., Electrical Engineering, Michigan State University
1. M. Thornton, P. Gui, T. Manikas, “Security Enhanced CAN Bus Transceiver Research”, Toyota Motors North America (TMNA), 7/1/22 – 6/30/24, $538,032
2. J. Dworak, T. Manikas, K. Nepal (U. St. Thomas), "Harvesting Wasted Time and Existing Circuitry for Efficient Field Testing ", National Science Foundation (NSF) CCF-1814928, 10/1/18 - 9/30/23, SMU amount $391,769, UST amount $93,491
1.
Faculty researcher on project “CAN Bus
Packet Authentication Research, Toyota Motors North America, May 1, 2020 - June
30, 2022
2.
Faculty researcher on project
"Quantum Informatics Research to Support Secure Communications and
Computation". Funded by Anametric, Inc., Aug. 1,
2020 through December 31, 2021, PI: M. Thornton, Co-PI: D. MacFarlane.
3. T. Manikas, M. Thornton, “DOD Information Assurance Scholarship Program”, Department of Defense H98230-18-1-0313, 8/1/18 - 7/31/19, $102,007
4. F. Chang, M. Thornton, T. Manikas, “Research and Investigation on Contractor Cyber Risk”, ISN, 9/1/18 – 8/31/19, $100,000
5. S. Nair, T. Manikas, “DOD Information Assurance Scholarship Program”, Department of Defense (DoD IASP H98230-16-1-0333), 9/13/16 - 9/12/17, $71,803.
6. S. Nair, T. Manikas, “DOD Information Assurance Scholarship Program”, Department of Defense (DoD IASP H98230-15-1-0327), 8/1/15 – 7/31/16, $60,126.
7. S. Nair, T. Manikas, M. Thornton, “DOD Information Assurance Scholarship Program”, Department of Defense (DoD IASP H98230-14-1-0296), 8/1/14 – 7/31/15, $61,936.
8. J. Dworak, P. Gui, T. Manikas, “High-Bandwidth Built-in Self Test for 3D ICs using Programmable Logic”, SMU Lyle School of Engineering Seed Funding, 4/1/14 – 12/31/14, $15,810.
9. S. Nair, T. Manikas, M. Thornton, “DOD Information Assurance Scholarship Program”, Department of Defense (DoD IASP H98230-13-1-0425), 9/6/13 – 9/5/14, $66,813.
10. S. Nair, M. Thornton, T. Manikas, “DOD Information Assurance Scholarship Program”, Department of Defense (DoD IASP H98230-11-1-0446), 9/26/11 – 12/25/12, $54,871.
11. M. Thornton, T. Manikas, “Radiation Hardened Standard Cell Library Design and Benchmarking Research”, Silicon Space Technology.
12. S. Nair, M. Thornton, T. Manikas, “Capacity Building for Security Architecture and Infrastructure for Smart-Grids”, Department of Defense (DoD IASP H98230-09-1-0396), 9/10/10 – 2/9/12, $69,632.
13. “Investigative Methods of Establishing Hardware Trust Centers with a Focus on Detection of Trojans at the Register Transfer Level (RTL) During the Device Design Stage”, Lockheed-Martin Aerospace, Fort Worth, Texas, June 30, 2011 - May 31, 2012.
14. “Secure Smart Meter Firmware Research and Development”, PayGo Electric, Alpharetta, Georgia, September 2010 - May 2011.
15. “Smart Meter & DPA Resistant Encryption Research”, Revere Security, Dallas, Texas, October 2010-August 2011.
CS 2353 Discrete Computational Structures
CS 4381/ECE 3382 Digital Computer Design
CS 5380/7380 VLSI Algorithms
CS/ECE 5381/7381 Computer Architecture
CS 7311 Foundations of Computing
CS 7390 Special Topics: Applications of Random Number Generation (independent study)
EE 2161 Digital Design Laboratory
EE 2163 Digital Design Principles
EE 3113 Signals and Linear Systems
EE 4073 Information and Communications Systems
EE 4143/6443 VLSI Design
EE 7063 Computer Engineering
EE 7993 VLSI Design Automation (independent study)
EE 7993 VLSI Logic Synthesis (independent study)
EE 7993 VLSI Physical Synthesis (independent study)
· Computer Science Graduate Admissions Coordinator and Adviser, 2020 - present
· Computer Science Faculty Search Committee, 2019 - present
· Chair, Computer Science Graduate Program Committee, 2019 - present
· Chair, Computer Science Undergraduate Program Committee, 2019– present
· Chair, Computer Science TA Selection Committee, 2019 – present
· Lyle Graduate Marshal, May Commencement, 2023
· Judge for Graduate Posters, Research and Innovation Week, 2023
· Computer Science Department Coordinator Selection Committee, 2022
· Computer Science MS Bridge Program Committee, 2022
· Undergraduate Adviser, Computer Science, 2019 - 2020
· Computer Science and Engineering Faculty Search Committee, 2017 - 2018
· Undergraduate Adviser, Computer Engineering and Computer Science Security Track, 2014 - 2018
· Chair, Computer Science and Engineering Graduate Program Committee, 2010 - 2018
· Chair, Computer Science and Engineering Undergraduate Program Committee, 2012 – 2018
· Chair, Computer Science and Engineering TA Selection Committee, 2012 – 2018
· Computer Engineering Graduate Admissions Coordinator, 2012 - 2018
· Lyle College of Engineering Assessment Committee, 2011 – 2018
· Hunt Leadership Scholarship Application Review Panel, 2017
· Digital Repository Advisory Board, 2012 - 2014
· University representative for the Synopsys Curricula Advisory Board, 2010 – 2015
· Computer Science and Engineering Industry Advisory Board Liaison, Curriculum and Technology, 2011 – 2012
· Session Judge, Graduate Research Colloquium, 2011, 2013
· International Conference on Design and Modeling in Science, Education, and Technology
1. Micah Thornton, M.S., Computer Engineering, 2017, “Randomness Properties of Cryptographic Hash Functions”
Computer Science: Gerald Shaffer, Xiaodian Xie, Samuel Hunter, Joshua Sylvester
Computer Engineering:, David Houngninou, Adam Zygmontowicz, Phillip Morris, Yi Sun, Sravana Kancharla, Michael Taylor
Electrical Engineering: Nisharg Shah, Chi Zhang, Lakshmi Ramakrishnan, Tao Fu
1. Xianshan Wen, Ph.D., Electrical Engineering
2. Nisharg Shah, Ph.D., Electrical Engineering, 2023
3. Rob Oshana, Ph.D., Computer Science, 2023
4. Hui Jiang, Ph.D., Computer Engineering, 2022
5. Liang Fang, Ph.D., Electrical Engineering, 2021
6. Yi Sun, Ph.D., Computer Engineering, 2021
7. Chang Yang, Ph.D., Electrical Engineering, 2020
8. Xiaoran Wang, Ph.D., Electrical Engineering, 2020
9. Eman Ababtain, Ph.D., Computer Science, 2020
10. Qutaiba Khasawneh, Ph.D., Electrical Engineering, 2019
11. Kaitlin Smith, Ph.D., Electrical Engineering, 2019
12. Sherry Huang, Ph.D., Electrical Engineering, 2019
13. Rita Enami, Ph.D., Electrical Engineering, 2019
14. Stephen Hanka, D.E., Software Engineering, 2019
15. Abdullah Bokhary, Ph.D., Computer Science, 2018
16. Kexu Sun, Ph.D., Electrical Engineering, 2018
17. Guanhua Wang, Ph.D., Electrical Engineering, 2018
18. Fanchen Zhang, Ph.D., Computer Engineering, 2018
19. David Houngninou, Ph.D., Computer Engineering, 2017
20. Soha Alhelaly, Ph.D., Computer Science, 2017
21. Adel Alharbi, Ph.D., Computer Engineering, 2017
22. Isaac Chow, D.E., Software Engineering, 2017
23. Mihai Tudor Panu, Ph.D., Computer Science, 2014
24. John J. Howard, Ph.D., Electrical Engineering, 2014
25. Anurag Nagar, Ph.D., Computer Science, 2013
26. Siling Wang, Ph.D., Computer Science, 2011
27. Lun Li, Ph.D., Computer Engineering, 2006
(Electrical Engineering)
Electrical Engineering: Yan Yu, Dong Xiang, Men Long, Su Yang, Sidharth Thakur, Gautam Ramamurthy, Jagruthi Godugu, Like Zhang, Alagappan S. Alagappan, Jovonia Taylor, Tuan Huynh
Computer Science: Samuel East, Arun Seelagan, Aaron Engel, Michael Spainhower, Denise Grayson, Christopher McVay, Donald Jung
1. “System Threats with Conditional Probabilities: Analysis using Multiple-Valued Logic Decision Diagrams”, Graduate Seminar, Southern Methodist University, October 3, 2012.
2. “A Pareto-Optimal Genetic Algorithm for Channel Routing in Integrated Circuits”, Graduate Seminar, Southern Methodist University, February 1, 2012.
3. “Using Multiple-Valued Logic Decision Diagrams to Analyze System Threats”, Graduate Seminar, Southern Methodist University, October 12, 2011.
4. “Genetic Algorithms and their Applications to Engineering Problems”, Graduate Seminar, Southern Methodist University, March 31, 2011.
5. “Genetic Algorithms and their Applications to Engineering Problems”, Graduate Seminar, Computer Science, University of Texas at Dallas, December 15, 2010.
6. “Axiomatic Analysis and Cyber Threat Tree Models for the Development of Large-Scale Disaster-Tolerant Systems”, IEEE Computer Society Meeting, Texas Instruments, Dallas, Texas, June 18, 2010.
7. “VLSI and Nanotechnology Circuit Design for Mixed-Signal Sensor Systems”, Graduate Seminar, Southern Methodist University, October 1, 2009.
1. H. Jiang, F. Zhang, J. Dworak, K. Nepal and T. Manikas, "Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift", Journal of Electronic Testing: Theory and Applications (JETTA), 39(2), 227–243.
2. S. Alhelaly, J. Dworak, K. Nepal, T. Manikas, P. Gui and A. L. Crouch, "3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 774-786, 1 April-June 2021.
3. Y. Sun, F. Zhang, H. Jiang, K. Nepal, J. Dworak, T. Manikas, R.I. Bahar, “Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack”, Journal of Electronic Testing: Theory and Applications (JETTA), Dec. 2019.
6. S. Nagayama, T. Sasao, J. Butler, M. Thornton and T. Manikas, “On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems”, IEICE Transactions on Information and Systems, Vol.E97-D, No.9, pp.2234-2242, Sep. 2014.
7. T.W. Manikas, “Integrated Circuit Channel Routing Using a Pareto-Optimal Genetic Algorithm”, Journal of Circuits, Systems, and Computers, vol. 21, no. 5, Aug. 2012.
8. T.W. Manikas, L.L. Spenner, P.D. Krier, M.A. Thornton, S. Nair, and S.A. Szygenda, “An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling”, Journal of Systemics, Cybernetics and Informatics, vol. 9, no. 1, 2011, pp. 89-93.
9. D. Chatterjee and T.W. Manikas, "On-Chip Thermal Optimisation by Whitespace Reallocation using a Constrained Particle-Swarm Optimisation Algorithm", IET Circuits, Devices, and Systems, vol. 4, no. 3, May 2010, pp. 251-260.
1. E.
Yassien, Y. Xu, H. Jiang, T. Nyugen,
J. Dworak, T. Manikas, and K. Nepal, “Harvesting Wasted Clock Cycles for
Efficient Online Testing”, 2023 IEEE European Test Symposium (ETS), Venezia,
Italy, 2023, pp. 1-6.
2. H. Jiang, J. Dworak, K. Nepal and T. Manikas, "Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift," 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS), 2022, pp. 1-6.
3. A. Sinha, M. Taylor, N. Srirama, T. Manikas, E. C. Larson and M. A. Thornton, "Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus," 2021 IEEE Conference on Control Technology and Applications (CCTA), 2021, pp. 693-700.
4. Y. Sun, H. Jiang, L. Ramakrishnan, J. Dworak, K. Nepal, T. Manikas, R.I. Bahar, “Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits”, 2021 IEEE International Test Conference (ITC), pp. 319-323.
5. Y. Sun, H. Jiang, L. Ramakrishnan, M. Segal, J. Dworak, T. Manikas, K. Nepal, R.I. Bahar, “Test Architecture for Fine Grained Capture Power Reduction”, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genova, Italy, November 2019
6. T.W. Manikas and M.A. Thornton, “Model Checking for Security Analysis of Cyber-Physical Systems”, 2nd International Conference on Data Intelligence and Security (ICDIS 2019), South Padre Island, TX, USA, June 2019
7.
K. N. Smith, M. A. Taylor, A. A.
Carroll, T. W. Manikas and M. A. Thornton, "Automated Markov-chain based
analysis for large state spaces," 2017 Annual IEEE International Systems
Conference (SysCon), Montreal, QC,
Canada, 2017, pp. 1-8.
8. P.C. Davis, M.A. Thornton, T.W. Manikas, “Reliability Block Diagram Extensions for Non-Parametric Probabilistic Analysis”, Proc. 10th Annual IEEE Systems Conference (SysCon), April 2016, pp. 927-932.
9.
T.W. Manikas, M.A. Thornton, S. Nagayama, “An
Improved Methodology for System Threat Analysis Using Multiple-Valued Logic and
Conditional Probabilities”, Society for
Design and Process Science Conf. (SDPS
2015), Nov. 2015.
10.
S. Nagayama, T. Sasao,
J. Butler, M. Thornton, and T. Manikas, “Edge Reduction for EVMDDs to Speed Up
Analysis of Multi-State Systems”, Proc.
45th IEEE International Symposium
on Multiple-Valued Logic, May 2015, pp. 170-175.
11. M. Thornton, T. Manikas, S. Szygenda and S. Nagayama, "System Probability Distribution Modeling using MDDs", 44th IEEE International Symposium on Multiple-Valued Logic, May 2014, pp. 196-201.
12. S. Nagayama, T. Sasao, J. Butler, M. Thornton and T. Manikas, "Analysis Methods of Multi-State Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams", 44th IEEE International Symposium on Multiple-Valued Logic, May 2014, pp. 190-195.
13. K. Nepal, X. Shen, J. Dworak, T. Manikas, R.I. Bahar, “Built-in Self-Repair in a 3D Die Stack Using Programmable Logic”, 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct. 2013, pp. 243-248.
19. T.W. Manikas, L.L. Spenner, P.D. Krier, M.A. Thornton, S. Nair, and S.A. Szygenda, “An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling”, Proc. Int. Multi-Conf on Complexity, Informatics, and Cybernetics (IMCIC’10), Int. Institute of Informatics and Systemics (IIIS), April 6-10, 2010, Orlando, Florida, USA, pp. 66 – 70, (best paper award).
1. Y.
Sun, H. Jiang, L. Ramakrishnan, M. Segal, J. Dworak, K. Nepal, T. Manikas, and
R. I. Bahar, “Scan Segment Disable for Capture Power
Reduction for Low-Power Decompressed Patterns”, 2019 IEEE North
Atlantic Test Workshop (NATW), Essex, VT, USA, May 2019 (Jake Karrfalt Best Student
Paper Award)
2.
S. Alhelaly, J. Dworak, T. Manikas, P.
Gui, K. Nepal and A. L. Crouch, "Detecting a Trojan die in 3D stacked
integrated circuits," 2017 IEEE North Atlantic Test Workshop
(NATW), Providence, RI, USA, May 2017, pp. 1-6.
3. F. Zhang, Y. Sun, X. Shen, K. Nepal, J. Dworak, T. Manikas, P. Gui, R.I. Bahar, A. Crouch, and J. Potter, “Using Existing Reconfigurable Logic in 3D Die Stacks for Test”, 25th IEEE North Atlantic Test Workshop, May 2016, (IEEE Excellence in Design and Test Engineering Award).
4. K. Nepal, X. Shen, J. Dworak, T. Manikas, R.I. Bahar, "Harnessing an FPGA for Built-in Self-Repair in a 3D Die Stack", 22nd IEEE North Atlantic Test Workshop, May 2013.
5. T.W. Manikas, M.A. Thornton, and F.R. Chang, "Mission Planning Analysis using Decision Diagrams", 2013 Reed Muller Workshop, May 2013.
6. S. Pham, J.L. Dworak, and T.W. Manikas, “An Analysis of Differences between Trojans inserted at RTL and at Manufacturing with Implications for their Detectability”, 2012 IEEE North Atlantic Test Workshop, May 2012.
7. T.W. Manikas and G.R. Kane, "Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement", Proceedings of the 11th IEEE/ACM International Workshop on Logic and Synthesis, 2002.
8. T.W. Manikas and G.R. Kane, "Standard Cell Partition Size Variance and its Effect on Physical Design", Proceedings of the 10th IEEE International Workshop on Logic and Synthesis, 2001.