Theodore W. Manikas - Publications

Computer Security and Disaster Tolerance

  1. A. Sinha, M. Taylor, N. Srirama, T. Manikas, E.C. Larson and M.A. Thornton, “Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus”, 2021 5th IEEE Conference on Control Technology and Applications (CCTA), 2021, pp. 693-700 (PDF).
  2. S. A. Alhelaly, J. Dworak, K. Nepal, T. Manikas, P. Gui and A. L. Crouch, "3D Ring Oscillator based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations," IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 774-786, 1 April-June 2021 (PDF).
  3. T.W. Manikas and M.A. Thornton, “Model Checking for Security Analysis of Cyber-Physical Systems”, 2nd International Conference on Data Intelligence and Security (ICDIS 2019), South Padre Island, TX, USA, June 2019.
  4. S. Alhelaly, J. Dworak, T. Manikas, P. Gui, K. Nepal and A. L. Crouch, "Detecting a Trojan die in 3D stacked integrated circuits," 2017 IEEE North Atlantic Test Workshop (NATW), Providence, RI, USA, May 2017, pp. 1-6, (PDF).
  5. K. N. Smith, M. A. Taylor, A. A. Carroll, T. W. Manikas and M. A. Thornton, "Automated Markov-chain based analysis for large state spaces," 2017 Annual IEEE International Systems Conference (SysCon), Montreal, QC, Canada, 2017, pp. 1-8, (PDF).
  6. P.C. Davis, M.A. Thornton, T.W. Manikas, “Reliability Block Diagram Extensions for Non-Parametric Probabilistic Analysis”, Proc. 10th Annual IEEE Systems Conference (SysCon), Apr. 2016, pp. 927-932, (PDF).
  7. T.W. Manikas, M.A. Thornton, S. Nagayama, “An Improved Methodology for System Threat Analysis Using Multiple-Valued Logic and Conditional Probabilities”, Proc. Society for Design and Process Science Conf. (SDPS 2015), Nov. 2015, (PDF).
  8. S. Nagayama, T. Sasao, J. Butler, M. Thornton and T. Manikas, "Edge Reduction for EVMDDs to Speed Up Analysis of Multi-State Systems", Proc. 45th IEEE International Symposium on Multiple-Valued Logic, May 2015, pp. 170-175, (PDF) .
  9. T.W. Manikas, M.A. Thornton, D.Y. Feinstein, "Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams", Journal of Multiple-valued Logic and Soft Computing, v.24.1-4, pp. 135-149, 2015, [Invited Paper].
  10. S. Nagayama, T. Sasao, J. Butler, M. Thornton and T. Manikas, "On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems", IEICE Transactions on Information and Systems, Vol. E97-D, No. 9, pp. 2234-2242, Sep. 2014, (PDF)
  11. M. Thornton, T. Manikas, S. Szygenda and S. Nagayama, "System Probability Distribution Modeling using MDDs", Proc. 44th IEEE International Symposium on Multiple-Valued Logic, May 2014, pp. 196-201, (PDF)
  12. S. Nagayama, T. Sasao, J. Butler, M. Thornton and T. Manikas, "Analysis Methods of Multi-State Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams", Proc. 44th IEEE International Symposium on Multiple-Valued Logic, May 2014, pp. 190-195, (PDF)
  13. T.W. Manikas, M.A. Thornton, and F.R. Chang, "Mission Planning Analysis using Decision Diagrams", 2013 Reed Muller Workshop, May 2013. (PDF)
  14. S. Pham, J.L. Dworak, and T.W. Manikas, "An Analysis of Differences between Trojans inserted at RTL and at Manufacturing with Implications for their Detectability", 2012 IEEE North Atlantic Test Workshop, (PDF)
  15. T.W. Manikas, D.Y. Feinstein, M.A. Thornton, "Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams", Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2012), May 2012, pp. 244-249. (PDF)
  16. T.W. Manikas, M.A. Thornton, D.Y. Feinstein, "Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities", Proc. 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL-11), May 2011, pp. 263-267. (PDF)
  17. T.W. Manikas, L.L. Spenner, P.D. Krier, M.A. Thornton, S. Nair, and S.A. Szygenda, "An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling", Journal of Systemics, Cybernetics and Informatics, vol. 9, no. 1, 2011, pp. 89-93. (PDF)
  18. T.W. Manikas, "Modeling of Large-Scale Disaster-Tolerant Systems", Society for Design and Process Science Conf. (SDPS 2010), June 2010. (PDF)
  19. T.W. Manikas, L.L. Spenner, P.D. Krier, M.A. Thornton, S. Nair, and S.A. Szygenda,"An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling", Int. Multi-Conf on Complexity, Informatics, and Cybernetics (IMCICÂ’10), April 2010, [Best Paper Award]. (PDF)
  20. P. Ongsakorn, K. Turney, M. Thornton, S. Nair, S. Szygenda, and T. Manikas,"Cyber Threat Trees for Large System Threat Cataloging and Analysis", IEEE Int. Systems Conference, April 2010. (PDF)
  21. L. Spenner, P. Krier, M. Thornton, S. Nair, S. Szygenda, and T. Manikas, "Large System Decomposition and Simulation Methodology Using Axiomatic Analysis", IEEE Int. Systems Conference, April 2010. (PDF)
  22. T.W. Manikas and M.A. Thornton, "Axiomatic Analysis and Cyber Threat Tree Models for the Development of Large-Scale Disaster-Tolerant Information Security Systems", 2010 Symposium on Information Systems and Computing Technology Network (ISaCTN), April 2010.

VLSI and Nanotechnology Circuit Design and Test

  1. A. Coyle, H. Jiang, J. Dworak, T. Manikas, and K. Nepal, “Dual Use Circuitry for Early Failure Warning and Test”, 25th International Symposium on Quality Electronic Design (ISQED'24), to appear.
  2. A. Coyle, H. Jiang, J. Dworak, T. Manikas, and K. Nepal, “Leveraging Canary Flip-Flops in MISR for Superior SDC Detection", Presented at DISCC 2023 (2nd Workshop on Data Integrity and Secure Cloud Computing) held in conjunction with the 56th International Symposium on Microarchitecture (MICRO 2023).
  3. A. Coyle, H. Jiang, J. Dworak, T. Manikas, and K. Nepal, “Why Should DFT Stop at Test? Reusing DFT in Functional Mode”, IMTR23: 2nd Workshop on Intelligent Methods for Test and Reliability, May 25-26, 2023, Venice, Italy
  4. E. Yassien, Y. Xu, H. Jiang, T. Nyugen, J. Dworak, T. Manikas, and K. Nepal, “Harvesting Wasted Clock Cycles for Efficient Online Testing”, 2023 IEEE European Test Symposium (ETS), Venezia, Italy, 2023, pp. 1-6, doi: 10.1109/ETS56758.2023.10173955.
  5. H. Jiang, F. Zhang, J. Dworak, K. Nepal and T. Manikas, "Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift", Journal of Electronic Testing: Theory and Applications (JETTA) , 2023, 39(2), 227–243. https://doi.org/10.1007/s10836-023-06060-z
  6. H. Jiang, J. Dworak, K. Nepal and T. Manikas, "Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift," 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS), 2022, pp. 1-6.
  7. Y. Sun, H. Jiang, L. Ramakrishnan, J. Dworak, K. Nepal, T. Manikas, R.I. Bahar, “Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits”, 2021 IEEE International Test Conference (ITC), pp. 319-323 (PDF).
  8. Y. Sun, F. Zhang, H. Jiang, K. Nepal, J. Dworak, T. Manikas, R.I. Bahar, “Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack”, Journal of Electronic Testing: Theory and Applications (JETTA), Dec. 2019 (PDF)
  9. Y. Sun, H. Jiang, L. Ramakrishnan, M. Segal, J. Dworak, T. Manikas, K. Nepal, R.I. Bahar, “Test Architecture for Fine Grained Capture Power Reduction”, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genova, Italy from 27-29, November 2019 (PDF)
  10. Y. Sun, H. Jiang, L. Ramakrishnan, M. Segal, J. Dworak, K. Nepal, T. Manikas, and R. I. Bahar, “Scan Segment Disable for Capture Power Reduction for Low-Power Decompressed Patterns”, 2019 IEEE North Atlantic Test Workshop (NATW), Essex, VT, USA, May 2019
  11. F. Zhang, Y. Sun, X. Shen, K. Nepal, J. Dworak, T. Manikas, P. Gui, R.I. Behar, A. Crouch, and J. Potter, “Using Existing Reconfigurable Logic in 3D Die Stacks for Test”, 25th IEEE North Atlantic Test Workshop, May 2016, (IEEE Excellence in Design and Test Engineering Award) . (PDF)
  12. K. Nepal, S. Alhelaly, J. Dworak, R.I. Bahar, T. Manikas, and P. Gui,"Repairing a 3D Die-Stack Using Available Programmable Logic", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, v. 34, n. 5, pp. 849-861, May 2015. (PDF)
  13. K. Nepal, X. Shen, J. Dworak, T. Manikas, R.I. Bahar, "Built-in Self-Repair in a 3D Die Stack Using Programmable Logic", 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct. 2013, pp. 243-248. (PDF)
  14. K. Nepal, X. Shen, J. Dworak, T. Manikas, R.I. Bahar, "Harnessing an FPGA for Built-in Self-Repair in a 3D Die Stack", 22nd IEEE North Atlantic Test Workshop, May 2013.
  15. M.A. Thornton and T.W. Manikas, "Spectral Response of Ternary Logic Netlists", Proc. 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2013), May 2013, pp. 109-116. (PDF)
  16. T.W. Manikas, "Integrated Circuit Channel Routing Using a Pareto-Optimal Genetic Algorithm", Journal of Circuits, Systems, and Computers, vol. 21, no. 5, Aug. 2012. (PDF)
  17. D. Chatterjee and T.W. Manikas, "On-Chip Thermal Optimisation by Whitespace Reallocation using a Constrained Particle-Swarm Optimisation Algorithm", IET Circuits, Devices, and Systems, Vol. 4, no. 3, May 2010, pp. 251-260. (PDF)
  18. D. Chatterjee, T.W. Manikas, I. Markov, "COOLER- A Fast Multiobjective Fixed-outline Thermal Floorplanner", Proc. 3rd Annual Austin Conf. on Integrated Systems and Circuits (ACISC-08), May 2008. (PDF)
  19. T.W. Manikas and D. Teeters, "Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells", Proc 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL-08), 2008, pp. 197-201.(PDF)
  20. P.C. Utekar, T.W. Manikas, and D. Teeters, "Nanobattery-crossbar system, a promising candidate for future nanoscale data storage", Proc. 213th ECS (ElectroChemical Society) Meeting, 2008.
  21. "Nanoscale Power and Memory Unit Design for Nanoscale Sensor Systems", T.W. Manikas and D. Teeters, Proceedings of the 53rd ISA Int. Instrumentation , 2007. (PDF)
  22. "A Genetic Algorithm for Non-Slicing Floorplan Representation", D. Chatterjee and T.W. Manikas, Proceedings of National Conference on Intelligent Systems (NCIS), 2007. (PDF)
  23. "Power-Density Aware Floorplanning for Reducing Maximum On-Chip Temperature", D. Chatterjee and T.W. Manikas, Proceedings of 18th IASTED International Conference on Modelling and Simulation (ICMS), pp. 319-324, 2007. (PDF)
  24. C.M. Linnet and T.W. Manikas, "A Genetic Algorithm for Binary Decision Diagram Variable Ordering", Proceedings of the 81st AAAS-SWARM Annual Meeting, 2006.
  25. T.W. Manikas and G.R. Kane, "Partitioning Effects on Placement Performance for VLSI Design", Proceedings of the 78th AAAS-SWARM Annual Meeting, 2003.
  26. T.W. Manikas and M.H. Mickle, "A Genetic Algorithm for Mixed Macro and Standard Cell Placement", Proc. 45th IEEE Int. Midwest Symp. on Circuits and Systems, 2002, p. 115-118. (PDF)
  27. L. Li, T.W. Manikas, and H. Jin, "Channel Height Estimation in VLSI Design", Proc. 45th IEEE Int. Midwest Symp. on Circuits and Systems , 2002, p. 611-614. (PDF)
  28. T.W. Manikas and G.R. Kane, "Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement", Proc. 11th IEEE/ACM Int. Workshop on Logic & Synthesis (IWLS '02), 2002, p. 27-30. (PDF)
  29. T.W. Manikas and G.R. Kane, "Standard Cell Partition Size Variance and its Effect on Physical Design", Proc. 10th IEEE Int. Workshop on Logic & Synthesis (IWLS '01), 2001, p. 265-268. (PDF)
  30. T.W. Manikas and J.T. Cain, "Genetic Algorithms vs. Simulated Annealing: A Comparison of Approaches for Solving the Circuit Partitioning Problem", Tech. Report TR-96-101, University of Pittsburgh, Dept. of Electrical Engineering, May 1996. (PDF)

Engineering Education

  1. M.A. Thornton, T.W. Manikas, and P.A. Laplante, "Embedded and Real-time Systems Classes in Traditional and Distance Education Format", Proc. 43rd Annual Frontiers in Education Conf. (FIE 2013), Oct. 2013, pp. 1379-1385. (PDF)
  2. P. LoPresti, T.W. Manikas, and J. Kohlbeck, "An Electrical Engineering Summer Academy for Middle School and High School Students", IEEE Transactions on Education, vol. 53, no. 1, Feb. 2010, pp. 18-25.(PDF)
  3. P. G. LoPresti, T.W. Manikas, J. Kohlbeck, "An Electrical Engineering Summer Academy for Middle School and High School Students", Proceedings of the 2008 ASEE Midwest Section Conference, 2008.
  4. T.W. Manikas and K. Ashenayi, "Industry-University Partnerships for Undergraduate Engineering Internships", Proceedings of the 2008 ASEE Midwest Section Conference, 2008. (PDF)
  5. "Developing and Funding Undergraduate Engineering Internships", T.W. Manikas and G.R. Kane, Proceedings of the 2007 ASEE Midwest Section Conference, 2007. (PDF)
  6. "Developing Laboratory Courses in a Resource-Constrained Environment", T.W. Manikas, D.E. Jussaume, and G.R. Kane, Proceedings of the 2005 ASEE Midwest Section Conference, University of Arkansas, Sept. 14-16, 2005. (PDF)
  7. "Developing Graduate Research Skills using Guided Reading Assignments", T.W. Manikas and G.R. Kane, Proc. 39th ASEE Midwest Section Conf., 2004. (PDF)
  8. "A VLSI Design Course in a Resource-Constrained Environment", T.W. Manikas and G.R. Kane, Proc. 38th ASEE Midwest Section Conf., 2003. (PDF)
  9. "A Digital Logic Design Laboratory for Electrical Engineering and Computer Science Undergraduates", T.W. Manikas, G.R. Kane, and J.G. Kohlbeck, Proc. 37th ASEE Midwest Section Conf., 2002. (PDF)
  10. "A Senior Design Course That Simulates an Industrial Engineering Environment", M.O. Durham and T.W. Manikas, Proc. 36th ASEE Midwest Section Conf., 2001. [Best Paper Award] (PDF)

Other Research Articles

  1. K. H-Sedighi, K. Ashenayi, T.W. Manikas, and R.L. Wainwright, "A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths", Int. Journal of Robotics and Automation, vol. 24, no. 4, 2009, pp. 367-373.
  2. B. Gahring, T. Manikas, and K. Ashenayi, "Developing an Autonomous Robot Navigation System Using Genetic Algorithms", Proceedings of the 2009 AAAS-SWARM Annual Meeting, 2009.
  3. M. Samiee, K. Ashenayi, and T. Manikas, "Investigation of Characteristics of Production Pipe as Related to Data Communication in an Oil Well", Proceedings of the 2009 AAAS-SWARM Annual Meeting, 2009.
  4. T.W. Manikas, K. Ashenayi, R.L. Wainwright, "Genetic Algorithms for Autonomous Robot Navigation", IEEE Instrumentation & Measurement Magazine, vol. 10, no. 6, Dec. 2007, pp. 26-31. [Invited Paper] (PDF)
  5. D.A. Ashlock, T.W. Manikas, and K. Ashenayi, "Evolving a Diverse Collection of Robot Path Planning Problems", Proc. 2006 IEEE Congress on Evolutionary Computation (CEC2006), p. 1837-1844 (PDF)
  6. A. Hand, J. Godugu, K. Ashenayi, T.W. Manikas, and R.L. Wainwright, "Benchmarking of Robot Path Planning Algorithms", in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering Systems Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Complex Systems and Artificial Life, C.H. Dagli, et al., Editors. 2005, ASME Press: New York. pp. 377-83. (PDF)
  7. A. Hermanu, T.W. Manikas, K. Ashenayi, and R.L. Wainwright, “Autonomous Robot Navigation Using a Genetic Algorithm with an Efficient Genotype Structure”, in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering Systems Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Complex Systems and Artificial Life, C.H. Dagli, et al., Editors. 2004, ASME Press: New York. pp. 319-324. (PDF)
  8. K. H-Sedighi, K. Ashenayi, T.W. Manikas, R.L. Wainwright, H.M. Tai, "Autonomous Local Path Planning for a Mobile Robot Using a Genetic Algorithm", Proc. 2004 IEEE Congress on Evolutionary Computation (CEC2004), p. 1338-1345. (PDF)
  9. T. Geisler and T.W. Manikas, "Autonomous Robot Navigation System Using a Novel Value Encoded Genetic Algorithm", Proc. 45th IEEE Int. Midwest Symp. on Circuits and Systems, 2002, p. 45-48. (PDF)
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