WEEK |
DATE |
EVENTS/HOLIDAYS |
READING, HOMEWORK, AND LAB EXPERIMENTS |
CLASS TOPIC AND OVERHEADS |
Week 1 |
26-Aug |
First Day of Class |
NO LAB THIS WEEK
Sections 1-1 through 1-4 |
Class Introduction
Number Systems |
Week 2 |
31-Aug
|
Tuesday Sept. 01 :
Last day to enroll, add, or drop without grade change or tuition billing
Last day to file for December graduation |
NO LAB THIS WEEK
Sections 1-5 through 1-7
Homework 1-3, 1-9,
1-12, 1-13, 1-14, 1-15, 1-16, 1-17
DUE AT BEGINNING OF CLASS ON SEP. 14 |
More Number Systems |
|
02-Sep
|
|
Sections 1-8 through 1-9
|
Signed Numbers |
Week 3 |
07-Sep |
Holiday - Labor Day
NO CLASS |
NO LAB THIS WEEK
NO CLASS
| NO CLASS |
|
09-Sep |
Friday Sept. 11 :
Last day to request excused absence for observance of a religious holiday
|
Sections 2-1 through 2-4 |
Binary Codes |
Week 4 |
14-Sep |
|
LAB EXPERIMENT 1
Lab Equipment Notes
HOMEWORK DUE
Section 2-5 through 2-7
Homework 2-1, 2-3, 2-6, 2-10, 2-18, 2-21
DUE AT BEGINNING OF CLASS ON SEP. 28
|
Logic and Registers |
|
16-Sep |
|
Sections 2-8 and 3-1 through
3-3. |
Boolean Algebra |
Week 5
|
21-Sep |
|
LAB EXPERIMENT 2
Sections 3-4 through 3-6
|
Canonic and Standard Forms |
|
23-Sep |
|
Section 3-8 through 3-9
|
Logic Gates and Minimization |
Week 6 |
28-Sep |
|
LAB EXPERIMENT 3
HOMEWORK DUE
Homework 3-4; 3-6;
3-16, 3-21, 3-22
DUE AT BEGINNING OF CLASS ON OCT. 14 |
POS Gate-level Minimization |
|
30-Sep |
|
|
Discrete Event Simulation |
Week 7 |
05-Oct |
|
LAB EXPERIMENT 4
|
Verilog Introduction-Modules and Primitives |
|
07-Oct |
|
|
Verilog Introduction-Modules and Primitives |
Week 8 |
12-Oct |
Holiday - Fall Break
NO CLASS |
LAB EXPERIMENT 5
Section 3-10 and electronic notes
|
NO CLASS |
|
14-Oct |
|
HOMEWORK DUE |
Verilog Introduction-Modules and Primitives
|
Week 9 |
19-Oct |
|
LAB EXPERIMENT 5 (continued)
Cadence Verilog and Waveform Viewing Tutorial (Vista with Cygwin)
Cadence Verilog and Waveform Viewing Tutorial (XP with Exceed) |
Combinational Logic and Arithmetic Circuits |
|
21-Oct |
|
READING: Section 4-1 to 4-6 |
EXAM 1 REVIEW |
Week 10 |
26-Oct |
|
LAB EXPERIMENT 6
READING: Section 4-7 to 4-12
HOMEWORK: 3-33;
3-36; 4-5; 4-25; 4-27; 4-32
DUE AT BEGINNING OF CLASS ON NOV. 9
|
EXAM 1
|
|
28-Oct |
|
READING: Section 5-1 to 5-2 |
Combinational Building Blocks
|
Week 11
|
02-Nov |
|
LAB EXPERIMENT 7
READING: Section 5-3 to 5-5
add.v
ripple4.v
cla4.v
|
More Combinational Building Blocks
Synthesis Example using Synopsys Design Compiler |
|
04-Nov |
|
READING: Section 5-6 to 5-8
| Latches, Flip-flops and Characteristics |
Week 12 |
09-Nov |
|
LAB EXPERIMENT 8
HOMEWORK DUE
READING: Section 6-1 to 6-2
testmux.v
testdec.v
testdecprm.v
|
More Latches, Flip-flops and Characteristics and Examples |
|
11-Nov |
Tuesday Nov. 10: Last day to drop a course |
|
Synchronous Sequential Circuit Design |
Week 13 |
16-Nov |
|
LAB EXPERIMENT 9
HOMEWORK: 5-2; 5-6; 5-10; 5-17; 5-20 DUE AT BEGINNING OF CLASS ON NOV. 30
7400
74151
74157
|
More Synchronous Sequential Circuit Design |
|
18-Nov |
|
|
FSM Models and Verilog Descriptions |
Week 14 |
23-Nov |
|
NO LAB THIS WEEK
READING: Section 6-3 through 6-6
|
EXAM 2 Review
|
|
25-Nov |
NO CLASS |
NO CLASS |
NO CLASS |
Week 15 |
30-Nov |
|
LAB EXPERIMENT 10
HOMEWORK DUE
|
EXAM 2 |
|
02-Dec |
December 4-9: No final exams or unscheduled tests and papers |
READING: Chapter 7
HOMEWORK: 6-6; 6-18; 6-27; 7-1; 7-15; 7-21
DUE AT BEGINNING OF CLASS ON DEC. 09
|
Registers and Counters |
Week 16 |
07-Dec |
|
NO LAB THIS WEEK
|
Memory and Programmable
Logic
Exam 3 Review |
| EXAM 3 |
09-Dec |
EXAM 3 |
HOMEWORK DUE
EXAM 3 |
EXAM 3 |
NO FINAL EXAM |
Saturday
12-Dec |
NO FINAL EXAM
|
NO FINAL EXAM
|
NO FINAL EXAM
|
