// UDP for full-adder carry-out function
primitive coutprm (cout, a, b, cin);
    output cout;
    input  a, b, cin;
// Truth table for the carry-out function
    table
//   a  b  cin  :  cout
     0  0   0   :    0;
     0  0   1   :    0;
     0  1   0   :    0;
     0  1   1   :    1;
     1  0   0   :    0;
     1  0   1   :    1;
     1  1   0   :    1;
     1  1   1   :    1;
    endtable
endprimitive

// UDP for full-adder sum function
primitive sumprm (sum, a, b, cin);
    output sum;
    input  a, b, cin;
// Truth table for the sum function
    table
//   a  b  cin  :  sum


// PUT YOUR CODE HERE

    endtable
endprimitive

// Model a full-adder
module fadd (cout, sum, a, b, cin);
   output cout, sum;
   input  a, b, cin;
   wire   a, b, cin;  //Not necessary default type is wire
   wire   cout, sum;  //Not necessary default type is wire
   coutprm u1 (PUT PROPER NETS HERE);
   sumprm  u2 (PUT PROPER NETS HERE);
endmodule

// Model a 4-bit ripple adder
module ripple4(cout, sum, a, b, cin);
  output [3:0] sum;
  output cout;
  input  [3:0] a, b;
  input cin;

// YOUR CODE HERE - FOUR INSTANTIATIONS OF FADD

endmodule

// Testbench for 4-bit ripple adder
module ripple4test;
  reg [3:0] a, b;
  reg cin0;
  wire [3:0] sum;
  wire cout3;
  ripple4 u1 (cout3, sum, a, b, cin0);
  initial
     begin
       $stop;
       #10;
       a=4'h0; b=4'h0; cin0=1'b0;
       #10;
       a=4'hf; b=4'hf; cin0=1'b0;
       #10;
       a=4'h0; b=4'h0; cin0=1'b1;
       #10;
       a=4'hf; b=4'hf; cin0=1'b1;
       #10;
       a=4'h5; b=4'ha; cin0=1'b0;
       #10;
       a=4'h5; b=4'h5; cin0=1'b0;
       #10;
       a=4'ha; b=4'ha; cin0=1'b0;
       #10;
       a=4'h5; b=4'ha; cin0=1'b1;
       #10;
       a=4'ha; b=4'h5; cin0=1'b1;
       #10;
       a=4'h1; b=4'hf; cin0=1'b1;
       #10;
       a=4'hf; b=4'h1; cin0=1'b0;
       #10;
       a=4'h7; b=4'h7; cin0=1'b1;
       #10;
       a=4'h8; b=4'h7; cin0=1'b1;
       #10;
       $stop;
   end
endmodule