Home
    Research
    Teaching
    Papers
    Hacnet
    Kerala
    India
    Pics

Digital Logic Design

Spring 2002

Instructor - Padmaraj Nair.
Time - Thu 08AM - 11.50AM
- Fri 02PM - 04.50 PM
Place - 221EL
Office - SIC Room# 326
Phone - 214-768-3937
Email - mpadmara@seas.smu.edu
Office hours - Fri 01PM - 02PM
Grading policy - Labs 60% , Exam1 20%, Exam2 20%
Text books - Digital Design, 2nd edition, Prentice Hall
- The TTL Logic Data Book, Texas Instruments.

Lab1 - Introduction. 01/24/02 (Due 01/31/02) & 01/25/02 (Due 02/01/02)
Lab2 - 01/31/02 (Due 02/06/02) & 02/01/02 (Due 02/07/02)
Lab3 - - 01/31/02 (Due 02/13/02) & 02/01/02 (Due 02/14/02)
Exam1
Lab4 - 02/14/02 (Due 02/21/02) & 02/15/02 (Due 02/22/02)
Lab5 - 02/21/02 (Due 02/27/02) & 02/22/02 (Due 02/28/02)
Lab6 - 03/07/02 (Due 03/20/02) & 03/08/02 (Due 03/21/02)
Lab7 - 03/07/02 (Due 03/20/02) & 03/08/02 (Due 03/21/02)
Lab8 - 03/07/02 (Due 03/20/02) & 03/08/02 (Due 03/21/02)
Missing labs and homeworks.
Exam2.
Lab9 - 03/07/02 (Due 03/20/02) & 03/08/02 (Due 03/21/02)
Lab10 - 03/07/02 (Due 03/20/02) & 03/08/02 (Due 03/21/02)
Copyright 2003 ©Padmaraj Nair