SRC (2009-2012)

Semiconductor Research Corporation

High-Voltage Linear Amplifier for Ultrasonic Medical Instruments.

The aim of this project is to design an integrated high-voltage linear amplifier as the driver for ultrasonic transducers to enhance the ultrasonic imaging resolution and quality.

CERN (2007-2012)

European Organization for Nuclear Research

The GBTIA, a 5-Gbps Radiation-Tolerant Optical Transimpedance Amplifier for CERN SLHC, in collaboration with CPPM Marseille).

IC designed and fabricated in IBM 0.13µm CMOSRF process

Measured eye diagram at 5 Gbps.

SRC (2007-2010)

A Low-Jitter Frequency Synthesizer with Large Multiplication Factor N.

IC designed and fabricated in IBM 0.13µm CMOSRF process

Clock jitter measurement: rms jitter of 6.9ps at 1 GHz

CERN (2007-2012)

A Configurable Clock Phase Shifter with 50 ps Resolution for a Timing-Trigger-Control System for CERN’s SLHC Experiments.

IC design in IBM 0.13µm CMOSRF process; To be submitted for fabrication in Nov. 2009.

CERN (2008-2009)

An NMOS Low Dropout Voltage Regulator with Switched Floating Capacitor Gate Overdrive.

 IC designed in IBM 0.13µm CMOSRF process. To be fabricate in 2010.

The LDO has a 0.2V dropout at a 50 mA load. It occupies an area of 0.009 mm² and does not require any external component.

Dynamic response of the LDO to a worst case scenario full load step. The output variation when a full load step is applied is 300 mV and the recovery time is below 0.2 µs.

SRC ((2007-2010)

A Wide-Tuning-Range (250MHz-to-4GHz)

Σ-∆ fractional-N Frequency Synthesizer

IC designed in IBM 0.13µm CMOSRF process; To be submitted for fabrication in Nov. 2009.

Frequency range: 250MHz to 4Ghz. Waveforms of VCO output at 1GHz, bottom waveform; the frequency multiplier output at 2GHz and 4GHz (top two waveforms).

Peregrine Semiconductor Corp, University Research Council (2006-2008)

A Wide-band, Low-jitter and Radiation-Tolerant LCPLL.

IC designed and fabricated in 0.25µm Silicon-on-Sapphire CMOS technology.

The PLL has a central frequency of 3.0 GHz and a bandwidth of 1.2 GHz. The measurement results after total irradiation of 100 Krad (Si) show that the LCPLL has superior TID tolerance compared to a self-biased ring oscillator based PLL.

Measured frequency range (top) and jitter (bottom) before and after irradiation up to 100 Krad/s (Si).

NSF/ATLAS (2005-2008)

Link-on-Chip, a 2.5 Gbps laser driver for CERN ATLAS LAr front-end readout

IC designed and fabricated in 0.25µm Silicon-on-Sapphire CMOS technology.

Measured link eye diagram at 2.5 Gbps

CERN/ATLAS

(2005-2006)

Characterization of the TID and SEE Tolerance of Silicon-on-Sapphire CMOS Technology.

IC designed and fabricated in 0.25µm Silicon-on-Sapphire CMOS technology.

TID Characterization of the SOS technology.

Top: NMOS devices; Bottom: PMOS devices.