πRGA is an iterative switching algorithm that achieves high throughput even when the number of iterations drops to 1. πRGA is based on the iterative Request Grant Accept paradygm RGA. Most of the iterative RGA switching algorithms (except for iSLIP and DRR when the traffic is uniform) require multiple iterations to achieve high throughput.

Given a priority scheme π; the πRGA algorithm is as follows: πRGA algorithm

A special priority scheme that we use is the Earliest Activation Time. The activation time of a VOQ is the last time at which the VOQ became active (non-empty). In the simulations below, the number of iterations is limited to 1. The simulation shows the performance of πRGA in comparison to other known iterative switching algorithms. Below we show the comparison in performance under a Uniform traffic, a geometrically polarized traffic (Non-Uniform I), a traffic in which half the flows participate uniformly (Non-Uniform II), a traffic in which half the flows participate in a geometrically polarized way (Non-Uniform III), and a 16x16 switch (average of 100 simulations).

% Throughput (1 iteration)

	iSLIP	DRR	pDRR	PIM	iLQF	iOCF	πRGA
Uniform traffic	98.76	98.76	69.58	64.41	68.91	67.67	97.78
Non-Uniform traffic I	72.55	71.09	78.52	68.28	77.29	73.23	90.19
Non-Uniform traffic II	95.90	96.40	72.14	65.63	71.32	68.95	93.79
Non-Uniform traffic III	72.71	71.23	78.57	68.32	77.35	73.30	90.13

The motivation for the 1 iteration limit is theoretical: to make a very fast switch, that cannot afford to fit multiple iterations of the algorithm, achieve a high throughput. This also implies that one would be able to trade off performance and switching time (and possibly allow the switch to perform additional processing), without having much degradation in performance.

The key behind the πRGA algorithm is the stabilization of the matching (the matching of input ports to output ports), which makes it possible to grow the size of the matching with successive matching phases. Therefore, instead of computing a matching from scratch at the beginning of every matching phase (and hence not attaining a good size matching because of the 1 iteration limit), πRGA uses parts of the previously computed matching (by making requests that are granted and accepted Strong in the next time step).

Theoretically, πRGA achieves a bound O(N³) on the delay for every packet, with a switch speedup of 2 (i.e. switch is half loaded) and a traffic satisfying that the aggregate flow between every two ports has constant burst.