Publications

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Conference papers

Peter-M. Seidel and James Stine, Optimizing Parametric Generators for Verified VLSI Circuits, accepted for Asilomar Conference on Signals, Systems and Computers, 2006.
Nikhil Kikkeri and Peter-M. Seidel, Optimized Arithmetic Hardware Design with the Aid of Hierarchical Formal Verification, submitted to 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2006.
Sam Sandbote and Peter-M. Seidel, Control Flow Elaboration Cache, submitted to 13th IEEE International Symposium on High-Performance Computer Architecture, 2006.
Peter-M. Seidel, How to Optimize the Latency of Itanium FP Division at no extra Cost, accepted for Asilomar Conference on Signals, Systems and Computers, 2005. 
Ayewah, Nathaniel; Beyer, Sven; Kikkeri, Nikhil; and Seidel, Peter-M. Challenges in the Formal Verification of Complete State-of-the-Art Processors, to appear in Proc. IEEE International Conference on Computer Design (ICCD), IEEE Computer Society Press, 2005.
Kikkeri, Nikhil and Seidel, Peter-M. Formal Verification of Parametric Division Implementations, Proc. IEEE International Conference on Computer Design (ICCD), IEEE Computer Society Press, 2005.
Kikkeri, Nikhil and Seidel, Peter-M. Formal Co-Verification of Pipelined Datapaths, Proc. 48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE Computer Society Press, 2005.
Seidel, Peter-M. High-Radix Implementation of IEEE Floating-Point Addition, Proc. IEEE Int. Symposium on Computer Arithmetic (ARITH-17), pp.99-106, 2005.

Ayewah, Nathaniel and Seidel, Peter-M. Fused Models for Noise Reduction in Speech Processing, Proceedings of 38th Asilomar Conference on Signals, Systems and Computers, 2004.

Seidel, Peter-M. On-Line IEEE Floating-Point Multiplication and Division for Reduced Power Dissipation, Proceedings of 38th Asilomar Conference on Signals, Systems and Computers, 2004.

Bozinov, Daniel and Seidel, Peter-M. Iterative Gridding for Automated Microarray Image Analysis, Proceedings of 38th Asilomar Conference on Signals, Systems and Computers, 2004.

Kikkeri, Nikhil and Seidel, Peter-M. Formal Verification based on Signal Correlation Properties, Proceedings of IEEE Int. Conf. on Computer Design (ICCD), pp. 402-408, 2004.

Krueger, Steven D. and Seidel, Peter-M. Design of an On-line IEEE Floating-Point Addition Unit for FPGAs, Proceedings of FCCM, pp.239-246, 2004.

Seidel, Peter-M. and Fazel, Kenneth Two-dimensional Folding strategies for Improved Layouts of Permutation Networks & Cyclic Shifters , Proc. IEEE Int. Symposium on VLSI (ISVLSI), pp.277-278, 2004.

Seidel, Peter-M. Floating-Point Interlock Collapsing by Value Prediction, Partial Forwarding and Fused Operations, under review for ISCA 2004.

Marczynski, Ralph and Seidel, Peter-M. DiRAC: Dynamic Reconfiguration Animation and Control, 46th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE Computer Society Press, 2003.

Seidel, Peter-M. Multiple Path IEEE Floating-Point Multiply Accumulate, 46th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE Computer Society Press, 2003.

Seidel, Peter-M. Power-Delay Optimization with Logical Effort, Proceedings of the 37th Asilomar Conference on Signals, Systems & Computers, 2003.

Even, Guy and Seidel, Peter-M. Pipelined Multiplicative Division with IEEE Rounding, IEEE Int. Conference on Computer Design (ICCD), pp. 240-245, 2003.

Even, Guy and Seidel, Peter-M. and Ferguson, Warren E. A Parametric Error Analysis of Goldschmidt's Division Algorithm, Proceedings of the IEEE Int. Symposium on Computer Arithmetic (ARITH16), pp.165-172, 2003.

Venkataraghavan, V. and Nair, S. and Seidel, Peter-M., Simulation-based Validation of Security Protocols, Proc. of South Central Information Security Symposium (SCISS'03), 2003.

Seidel, Peter-M. Operand Modification Schemes for Reduced Power Multiplication, Proceedings of the 36th Asilomar Conference on Signals, Systems & Computers, pp. 52-56, 2002.

Seidel, Peter-M. Technology-Independent Delay Optimization of Complex CMOS Circuitries, Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE Computer Society Press, 2002.

Marczyinski, Ralph and Seidel, Peter-M. SDVV: Dynamic Visualization of VERILOG Simulations, Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE Computer Society Press, 2002.

Seidel, Peter-M. and McFearin, Lee and Matula, David W., Binary Multiplication Radix-32 and Radix-256, Proceedings of the 15th IEEE International Symposium on Computer Arithmetic (Arith15), IEEE Computer Society Press, pages 23-32, 2001.

Seidel, Peter-M. and Even, Guy, On the Design of Fast IEEE Floating-Point Adders, Proceedings of the 15th International Symposium on Computer Arithmetic (Arith15), IEEE Computer Society Press, pages 184-194, 2001.

Hillebrand, Mark and Schuerger, Thomas and Seidel, Peter-M., How to Halve Wire Lengths in the Layout of Cyclic Shifters, Proceedings of the IEEE International Conference on VLSI Design 2001, IEEE Computer Society Press, pages 339-344, January 2001.

Seidel, Peter-M., Exact Arithmetic based on Floating-Point Numbers, Proceedings Int. Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN2000), Karlsruhe, Germany, Sept.2000.

Seidel, Peter-M., On the Architecture of IEEE Compliant Floating-point Units, Proceedings of the 18th IASTED Conference on Applied Informatics, pages 260-268, February 2000.

Even, Guy and Seidel, Peter-M., A comparison of three rounding algorithms for IEEE floating-point multiplication , Proc. 14th International Conference on Computer Arithmetic (Arith14), IEEE Computer Society Press, pages 225-232, 1999.

Seidel, Peter-M., How to halve the latency of IEEE compliant floating-point multiplication , Proceedings of the 24^th EUROMICRO Conference, IEEE Computer Society Press, pages 329-332, 1998.

Seidel, Peter-M. and Even, Guy, How Many Logic Levels Does Floating-point Addition Require?, Proceedings of the International Conference on Circuit Design (ICCD98), IEEE Computer Society Press, pages 142-149, 1998.

Seidel, Peter-M., High-Speed Redundant Reciprocal Approximation , Proceedings of the 3rd Conference on Real Numbers and Computers (RNC3), vol. 3, pages 219-229, 1998.

Paul, Wolfgang J. and Seidel, Peter-M., On the Complexity of Booth Recoding , Proceedings of the 3rd conference on Real Numbers and Computers (RNC3), vol. 3, pages 199-218, 1998.

Even, Guy and Mueller, Sylvia M. and Seidel, Peter-M., A Dual Mode IEEE Multiplier , Proc. 2nd IEEE International Conference on Innovative Systems in Silicon (ISIS'97), IEEE Computer Society, pages 282-289, 1997.

Journal papers

Seidel, Peter-M., McFearin, Lee and Matula, David, Secondary Radix Recodings for Higher Radix Multipliers, IEEE Transactions on Computers (TC), Feb. 2005.

Even, Guy and Seidel, Peter-M. and Ferguson, Warren, A Parametric Error Analysis of Goldschmidt's Division Algorithm, Journal of Computer and System Sciences (JCSS), vol. 70, pages 118-139, Feb. 2005.

Seidel, Peter-M. and Even, Guy Delay-Optimized Implementation of IEEE Floating-Point Addition, IEEE Transactions on Computers, vol.53(2), pages 97-114, Feb. 2004.

Paul, Wolfgang J. and Seidel, Peter-M. To Booth or Not To Booth ?, INTEGRATION, the VLSI journal, vol. 32, pages 5-40, Nov. 2002.

Seidel, Peter-M. and Hillebrand, Mark and Schuerger, Thomas and Seidel, Reducing Wire Lengths in the Layout of Cyclic Shifters, IEICE Transactions, Special Section on VLSI and CAD Algorithms, Nov. 2001.

Even, Guy and Mueller, Sylvia M. and Seidel, Peter-M., A dual precision IEEE floating-point multiplier, INTEGRATION, the VLSI journal, vol. 29, pages 167-180, Sept. 2000.

Even, Guy and Seidel, Peter-M.,A comparison of three rounding algorithms for IEEE floating-point multiplication , IEEE Transactions on Computers, vol.49(7), pages 638-650, July 2000.

Seidel, Peter-M., High-Speed Redundant Reciprocal Approximation, INTEGRATION, the VLSI Journal 28(1999), pages 1-12.

Patents

Matula, David W. and Seidel, Peter-M. and McFearin, Lee, Higher Radix Multipliers with Simplified Partial Product Generators, US patent pending.

Seidel, Peter-M. and Even, G., Fast Floating-Point Adder and Rounder Design, US patent pending.

Seidel, Peter-M. and Even, G., Pipelined Multiplicative Division with IEEE Rounding, US patent pending.

Sam Sandbote and Peter-M. Seidel, Control Flow Elaboration Cache, US patent pending.

Thesis

Seidel, Peter-M., Selected Topics in Computer Arithmetic, Habilitation thesis, University of Saarland, Germany, December 2001.

Seidel, Peter-M., On the Design of IEEE Compliant Floating-Point Units and Their Quantitative Analysis, PhD thesis, University of Saarland, Germany, December 1999.

Seidel, Peter-M., Wavelet-based Learning Algorithms, Master's thesis, University of Hagen & GMD, Germany, August 1996.

Books

Seidel, Peter-M., Wavelet-based learning algorithms (in German), GMD-Studien Nr.298, ISBN 3-88457-298-9, 152 pages, 1996.