(current or under review or in preparation)
Title:
Abstract: With the
advent of new fabrication technologies, integrated circuit designs can utilize
more than hundred million gates that operate at frequencies in the GHz range.
It is generally assumed that current technology densities are already close to
physical limitations, and that there will not be much more performance gains to
expect from technology improvements. Additional performance will therefore have
to be found even more in the efficient utilization of parallelism. The large
increase in transistor count has significantly increased device complexities
allowing to implement entire complex systems on single chips (SoC) and even
massively parallel systems could fit on a single chip in the next chip
generations. When all components of a system are implemented in the same
technology on the same chip, integration issues become more significant in the
design process and interdependencies between components in the system increase
even in between design levels. The increasing chip complexities have an even
larger impact for designs on reconfigurable devices like FPGAs, which have been
very limited in their size in the past. For systems on complex reconfigurable
devices conventional design approaches are not sufficient to handle the
upcoming complexities, especially if the full dynamic potential of the
reconfigurable device should be accessible, if the basic structure of the
reconfigurable device should be utilized and if the overhead due to architectural
restrictions should be minimized. The research objectives of this project are
to develop modular design methodologies for dynamically reconfigurable
architectures with an emphasis on the application-specific adoption of the
levels of parallelism, to provide improved fundamental
understanding of the efficiency, interplay and adaptivity of parallelism
at several granularity levels and to quantitatively evaluate related trade-offs
in the design of complex systems for general SOC designs and in particular for
reconfigurable architectures.
Title:
Description: Call for Student Participation, for more info send mail to: seidel@engr.smu.edu
Title:
Abstract: For the growing complexity of current and future digital systems, the support of digital design by adequate CAD tools becomes increasingly important during all design phases. For specification of digital systems, hardware description languages (HDL) are widely used, Verilog [4] and VHDL being their most prominent representatives. For simulation and debugging of systems described in hardware description languages, there are numerous tools available that focus on computing and comparing values of selected signals, representing their behavior as waveforms or textual output over time. Alternative to a specification using HDLs, digital systems can also be described by schematic entry incorporating a graphical representation of their structure, interfaces and module dependencies. Schematic representations simplify discussing, analyzing and understanding a digital system, in particular to non-expert designers, but they are typically limited to designs of low complexity. Simulation tools considering schematic entry are very similar to those simulating HDL designs. The graphical structure available is conventionally not used for the simulations and it is our motivation to change this. For improved understanding of the behavior of digital systems we have developed the SDV2 (SMU Dynamic Verilog Visualization) tool, which serves as a front end for a conventional HDL simulator. Our tool enriches the HDL description of a system with schematic representations and animations for simulation and debugging. Regarding the input interface of the tool, we are particularly focusing on designs specified in Verilog. The SDV2 tool allows to schematically visualize the module structure of selected parts of the Verilog design. During simulation the signal propagations between module interfaces are animated as dynamic transitions in the schematics. This dynamic simulation visualization enhances conventional debugging of Verilog systems and simplifies the understanding of their dynamic behavior, which is useful both in educational and in industrial settings. In the DiRAC project we aim to extend the functionality of SDV2 to also animate and control dynamic reconfigurations of systems.
Title:
Abstract: In this Project we introduce and develop the theory of Holographic Codes and apply them in general communication systems.
Title:
Abstract: In this project we develop improved long arithmetic support for cryptography in hard- and software. The project is organized in cooperation with G&D and TAU
Title:
with Tool
Enhancement
Abstract: Curricula in Computer Science, Computer Engineering or Electrical Engineering typically contain a sequence of courses focusing on Digital Hardware Design. We are referring to this course sequence as the Hardware Track in the following. The Hardware Track typically consists of courses such as: Digital Logic Design, Assembly Language Programming, Computer Organization and Design, Computer Architecture, Processor Architecture and Interfacing and corresponding Labs for hands-on design experience in Digital and Computer Design. In this sequence, courses have to build on each other and later courses have to utilize material from earlier ones. By exploring the offerings of this long sequence of courses for the Hardware Track at numerous Universities we identify the following common inefficiencies:
1. The course sequence in the Hardware Track is presented in miscellaneous emphases, because the courses are taught by various faculty members and are often based on textbooks that are not directly related to each other.
2. The course content overlaps between the different courses: At the beginning of a course often review sessions are required, and for the development of more complex systems, the coverage of earlier design methodologies often needs to be repeated to unify students’ background.
3. Textbooks for different courses have different viewpoints on Hardware design and vary in notation, depth, emphasis and models used.
4. Although there is a huge variety of textbooks available for each of the topics to be covered in the Hardware Track, support by software tools or Web enhanced material essentially only exists for the most popular textbooks.
5. In the rare case that a course sequence for the Hardware Track is designed with carefully chosen interfaces, unified notation and models, it is difficult for external students with different background to join into the program.
This project aims at delivering improved support for streamlining and unifying the course offerings in the Hardware Track while still allowing for flexibility in the choice of textbooks, notation, depth and emphasis. To achieve this goal we explore the material from a large amount of textbooks with a focus on extracting the superset of material covered while abstracting from the orthogonal issues of notation, viewpoints and emphasis. These additional issues are then prepared for customization. An additional focus is on integrating models for quantitative analysis regarding several metrics, like delay, cost and power consumption, for use throughout the whole hardware track. This allows preparing students for detailed evaluations and optimizations in research components related to and integrated into the courses.
Title:
Abstract: The THEME project seeks to establish a sound scientific foundation for managing privacy, security and fault-tolerance in a world linked through computing and communication technology. This research is necessary to build secure and reliable mobile systems required in the heterogeneous environments of today's and tomorrow's highly interconnected, information technology enabled society. One of the main components in a network environment that supports mobile users is the infrastructure used by mobile hosts to communicate with other computers in the network. There is a wide spectrum of alternatives for the network infrastructures. The infrastructure could be entirely wired and stationary (e.g. Internet). Clearly, this is not suitable for situations that require great deal of flexibility such as battlefields, disaster locations, or remote areas. In other cases, the infrastructure could be completely wireless and mobile (e.g. ad hoc networks), which offers more flexibility and adaptation to the nature of the environment. The price for the added flexibility would be lower performance and less reliability and security. Between these two extremes, there are many levels of mobility and connectivity in a heterogeneous mobile environment, which might consist of stationary and mobile elements connected via wired and wireless links. The main objective of this proposal is to establish a trusted heterogeneous mobile environment, in which secure fault-tolerant communication routes can be guaranteed.
Title:
Abstract: It is often difficult to distinguish between the qualities of the technological realization of a complex circuit and the contribution of the underlying algorithm for the logic implementation. To extract these two qualities from each other, technology-independent analysis of circuitries becomes important. Technology-independent hardware models have often been accused of lacking level of detail in analyzing and treating design choices of the implementation. More detailed hardware models on the other hand often depend on the technology and process that is used for implementation. Recently, Sutherland et al. have introduced the hardware model of "logical effort" which allows a rigorous, but technology-independent treatment of gate delays, fanouts, optimized gate sizing and buffer insertion. This model has been introduced and used for small circuitries and simple paths. Our extension is the application of this model for technology-independent delay optimization of complex circuitries. The ThInGO project has the objective to further extend model, analysis and optimization to consider layouts of circuits including the consideration of wire effects. In addition to delay analysis and optimization, also circuit area and power dissipation are objectives to be analyzed and optimized.