CSE/EE  5/7387  Digital Systems Design
Fall 2009      Mon-Wed 11:00AM-12:20PM     Location: 307 Science Information Center
Laboratory    Sections:
                     N11C    Wed    1:00-2:50PM        Location: 306B Science Information Center
                     N12C    Thu     1:00-2:50PM        Location: 306B Science Information Center

CLASS INSTRUCTOR
Mitch Thornton, Expressway Tower, Office 800P, 214-768-1371, mitch@lyle.smu.edu

OFFICE HOURS
MW 7:00AM-10:00AM and 1:00PM-1:50PM or by appointment in 312 Science Information Center
 
DISABILITY ACCOMMODATIONS
Students needing academic accommodations for a disability must first contact Ms. Rebecca Marin, Coordinator, Services for Students with Disabilities (214-768-4557) to verify the disability and establish eligibility for accommodations.  They should then schedule an appointment with the instructor to make appropriate arrangements.  (See University Policy No. 2.4.)

OBSERVANCE OF RELIGIOUS HOLIDAYS
Religiously observant students wishing to be absent on holidays that require missing class should notify their instructors in writing at the beginning of the semester, and should discuss with them, in advance, acceptable ways of making up any work missed because of the absence.  (See University Policy No. 1.9.)

EXCUSED ABSENCES FOR UNIVERSITY EXTRACURRICULAR ACTIVITIES
Students participating in an officially sanctioned, scheduled University extracurricular activity will be given the opportunity to make up class assignments or other graded assignments missed as a result of their participation.  It is the responsibility of the student to make arrangements with the instructor prior to any missed scheduled examination or other missed assignment for making up the work.  (See the University Undergraduate Catalog).

LAB INSTRUCTOR/TEACHING ASSISTANT
John Howard, jjhoward@mail.smu.edu

LAB INSTRUCTOR OFFICE HOURS
Mon-Tue, 3:00PM-5:00PM in Science Information Center, Room 306B
 
TEXT
Introduction to Logic Synthesis Using Verilog HDL, Robert B. Reese and Mitchell A. Thornton, Morgan & Claypool Publishers , 2006, ISBN 10-1598291076 (errata).
Finite State Machine Datapath Design, Optimization, and Implementation, Justin Davis and Robert B. Reese, Morgan & Claypool, 2008, ISBN 1-59829-529-2.
Fundamentals of Digital Logic with Verilog Design, 2nd Edition, Stephen Brown and Zvonko Vranesic, Mc-Graw-Hill, 2007, ISBN 0-07-721164-2.

SOFTWARE
Download the Student Web Edition Software (v. 9.0) Directly from the Altera Website HERE. You will need to obtain a free license from the Altera website. The manual for the student edition software is located HERE. Note that in the laboratory and on the machines on campus, we are using the Professional Version of QuartusII which is version 5.0. The professional version has a lower version number than the web edition, but it is the latest version available.

Legacy versions of web edition Altera software available HERE

If the licensing is not set up correctly, please follow these steps:
1. Obtain a license file from the lab- license-new.dat - see the lab TA
2. Copy this file into C:/altera/quartus50
3. Open QuartusII
4. Tools >> License Setup
5. Redirect the "License file" option to point to: C:/altera/quartus50/license-new.dat

REFERENCE
1 .    HDL Chip Design, Douglas J. Smith, Doone Publications, 5th Edition, 1996, ISBN 0-9651934-3-8.

CATALOG DESCRIPTION
Modern topics in digital systems design including the use of HDLs for circuit specification and automated synthesis tools for realization.  Programmable logic devices are used throughout the course.  This course has heavy laboratory assignment content and a design project.

CO-REQUISITE
1. Digital Systems Design Laboratory Enrollment

PREREQUISITES
1. CSE 3381 - Digital Logic Design or EE 2381 Digital Computer Logic

ADMINISTRATION
Class Schedule
Grading Policy

TOPICS

• Digital Logic Design Review
• HDL (Discrete Event) Simulators
• Verilog Hardware Description Language (HDL)
• Combinational Logic Synthesis using Verilog
• Programmable Logic Architecture and LPMs
• Timing Constraints and Timing Models in Programmable Logic
• Pipelining for Increased Throughput
• Sequential Logic Synthesis using Verilog
• FSM State Assignment
• High Level Synthesis