JOURNAL ARTICLES

• Reversible Logic Synthesis Based on Decision Diagram Variable Ordering, Journal of Multiple-Valued Logic and Soft Computing, (to appear, with D.Y. Feinstein).
• Minimization of Quantum Multiple-Valued Decision Diagrams using Data Structure Metrics, Journal of Multiple-Valued Logic and Soft Computing, vol. 15, no. 4, pp. 361-377, (with D.Y. Feinstein and D.M. Miller).
• A Redundant Signed Binary Addition Based Digital-to-Frequency Converter, IEE Electronics Letters, vol. 45, no. 2, pp. 824-826, July 2009, (with W. Chen and P. Gui).
• A Discrete Logarithm Number System for Integer Arithmetic Modulo 2^k: Algorithms and Lookup Structures, IEEE Transactions on Computers, vol. 58, no. 2, Feb. 2009, pp. 163-174, (with A. Fit-Florea, L. Li, and D.W. Matula).
• A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 6, no. 4, 2008, (with D. Easton, V.S.S. Nair, and S.A. Szygenda).
• Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application Downtime & Executve Visibility, International Journal of Business Information Systems,vol. 3, no. 3, 2008, pp. 317-331, (with C.M. Lawler, M.A. Harper, and S.A. Szygenda).
• QMDD Minimization using Sifting for Variable Reordering, Journal of Multiple-Valued Logic and Soft Computing, vol. 13, no. 4-6, 2007, pp. 537-552, (with D.M. Miller and D.Y. Feinstein).
• Integrated Design Validation: Combining Simulation and Formal Verification in Integrated Circuit Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 4, no. 2, 2006, (with L. Li and S. Szygenda).
• A Coarse-Grain Phased Logic CPU, IEEE Transactions on Computers, vol. 54, no. 7, July 2005, pp. 788-799, (with R. B. Reese and C. Traver).
• Early Evaluation for Performance Enhancement in Phased Logic, IEEE Transactions on Computer Aided Design, (vol. 24, no. 4, pp. 532-550, April 2005, (with R. B. Reese, C. Traver, and D. Hemmendinger).
• Additive Bit-serial Algorithm for the Discrete Logarithm Modulo 2^k, IEE Electronics Letters, vol. 41, no. 2, pp. 57-59, January 2005, (with A. Fit-Florea and D.W. Matula).
• Addition-based Exponentiation Modulo 2^k, IEE Electronics Letters, vol. 41, no. 2, pp. 56-57, January 2005, ( with A. Fit-Florea and D.W. Matula).
• Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs, Journal of Multiple-Valued Logic and Soft Computing, vol. 10, no. 2, 2004, pp. 189-202, (with D. Michael Miller).
• Mixed-radix MVL Function Spectral and Decision Diagram Representation, Automation and Remote Control, vol. 65, issue 6, June 2004, pp. 1007-1017, (invited paper, in English and Russian).
• A Two-phase Micropipeline Control Wrapper with Early Evaluation, IEE Electronics Letters, vol. 40, no. 6, March 2004, pp. 365-366, (with R. B. Reese and C. Traver).
• A Fast Two-phase Micropipeline Control Wrapper for Standard Cell Implementation, IEE Electronics Letters, vol. 40, no. 4, February 2004, pp. 19-20, (with R. B. Reese and Cherrice Traver).
• Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor, Parallel Processing Letters, vol. 13, no. 3, September 2003, pp. 497-507.
• A Signed Binary Addition Circuit Based on an Alternative Class of Addition Tables, Computers & Electrical Engineering, vol. 29, no. 2, March 2003, pp. 303-315.
• Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation, Canadian Journal of Electrical and Computer Engineering, vol. 27, no. 4, October 2002, pp. 159-164, (invited paper, with R. Drechsler, M. Kerttu and P. Lindgren).
• Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs, VLSI Design, vol. 14, no. 1, February 2002, pp. 53-64, (with R. Drechsler and W. Günther).
• Boolean Function Representation and Spectral Characterization Using AND/OR Graphs, Integration, the VLSI Journal, vol. 29, September 2000, pp. 101-116, (with A. Žužek and R. Drechsler).
• Behavioral Synthesis of Combinational Logic Using Spectral Based Heuristics, ACM Transactions on Design Automation of Electronic Systems, vol. 4, no. 2, April 1999, pp. 219-230, (with V. S. S. Nair).
• Resource Estimation for Parallel Architectures with Distributed Processor/Memory Nodes, Journal of Computing and Information Technology, vol. 6, no. 4, December 1998, pp. 359-371 (with D. L. Andrews).
• Signed Binary Addition Circuitry with Inherent Even Parity Outputs, IEEE Transactions on Computers, vol. 46, no. 7, July 1997, pp. 811-816.
• BDD Based Spectral Approach for Reed-Muller Circuit Realisation, IEE Proceedings-Computers and Digital Techniques, vol. 193, issue 2, March 1996, pp. 145-150, (with V. S. S. Nair).
• Efficient Calculation of Spectral Coefficients and their Application, IEEE Transactions on Computer Aided Design, vol. 14, no. 11., November 1995, pp. 1328-1341, (with V. S. S. Nair).
• Efficient Calculation of Spectral Coefficients of Combinational Circuits, Digital Signal Processing: A Review Journal, October 1994, pp. 245-254, (with V. S. S. Nair).

BOOK CONTRIBUTIONS

• Multiple-Valued Logic Concepts and Representations, Morgan & Claypool Publishers, San Rafael, California, ISBN 10-1598291904 (hardcopy), 10-1598291912 (eBook), January 2008, (with D. M. Miller).
• Introduction to Logic Synthesis Using Verilog HDL, Morgan & Claypool Publishers, San Rafael, California, ISBN 10-1598291068 (hardcopy), ISBN 10-1598291076 (eBook), November 2006, (with R. B. Reese).
• Spectral Techniques in VLSI CAD, Kluwer Academic Publishers, Boston, Massachusetts, ISBN 0-7923-7433-9, July 2001 (with R. Drechsler and D. M. Miller).
• Multiprocessor Memory Resource Estimation, Chapter 10 in Parallel and Distributed Systems: Architectures, Tools and Algorithms, Jose Aguilar, Editor, IIIS Publishers, ISBN 980-07-5956-5, July 2001 (with D. L. Andrews).
• Computer-Aided Engineering and Design, Chapter 8 in ADVANCED ELECTRONIC PACKAGING: With Emphasis on Multi-Chip Modules, W. D. Brown, Editor, IEEE Press, Piscataway, New Jersey, ISBN 0-7803-4700-5, 1999, (with D. L. Andrews, J. M. Conrad and M. D. Glover).
• Microprocessor Systems, Article in the Encyclopedia of Life Support Systems, EOLSS Publishers Co. Ltd., March 2003.

PATENTS

• Method for Early Evaluation in Micropipeline Processors, Patent No. 7,043,710 B2, May 9, 2006, (Co-inventor with R.B. Reese).
• Determining a Table Output of a Table Representing a Hierarchical Tree for an Integer Valued Function, Patent Pending, Patent Application No. 20080005211, Filed June 26, 2007, (Co-inventor with D.W. Matula, A. Fit-Florea, and L. Li).

NATIONAL/INTERNATIONAL CONFERENCES

• An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling, International Conference on Computing, Communications and Control Technologies (CCCT), April 6-9, 2010, (to appear, with T. Manikas, L. Spenner, P. Krier, S. Nair, and S. Szygenda).
• A Digital-to-Frequency Converter using Redundant Signed Binary Addition, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2-5, 2009, pp. 495-498, (with W. Chen and P. Gui).
• A Low Power High Performance Radix-4 Approximate Squaring Circuit, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), July 7-9, 2009, pp. 91-97, (with S. Datla and D.W. Matula).
• On the Guidance of Reversible Logic Synthesis by Dynamic Variable Ordering, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 132-138, (with D. Feinstein).
• Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 256-261, (with S. Datla, L. Hendrix, and D. Henderson).
• A Low Power Radix-4 Dual Recoded Integer Squaring Implementation for use in Design of Application Specific Arithmetic Circuits, IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), October 26-29, 2008, pp. 1819-1822, (with J. Moore and D.W. Matula).
• Quantum Logic Implementation of Unary Arithmetic Operations, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 22-23, 2008, pp. 202-207, (with L. Spenner, D. W. Matula, and D. M. Miller).
• On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 22-23, 2008, pp. 138-143, (with D. Y. Feinstein and D. M. Miller).
• Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits, Proceedings of the IEEE/ACM Design, Automation and Test in Europe (DATE), March 10-14, 2008, pp. 1378-1381, (with D. Y. Feinstein and D. M. Miller).
• UML to SystemVerilog Synthesis for Embedded System Models with Support for Assertion Generation, Proceedings of the ECSI Forum on Design Languages, September 18-20, 2007, Paper 10 on CD-ROM, (with L. Li and F. Coyle).
• ESOP-based Toffoli Gate Cascade Generation, Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, August 22-24, 2007, pp. 206-209, (with K. Fazel and J.E. Rice).
• Axiomatic Design in the Biomedical Device Industry, Proceedings of the 11^th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007, (with D. Easton, V.S.S. Nair, and J. Stracener).
• Axiomatic Design Process for Disaster Tolerance, Proceedings of the 11^th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007, (with D. Easton and V.S.S. Nair).
• Variable Reordering and Sifting for QMDD, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 2B, paper 1, (with D. Michael Miller and D.Y. Feinstein).
• Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 8B, paper 2, (with M. Amoui, D. Grosse, and R. Drechsler).
• Techniques for Disaster Tolerant Information Technology Systems, IEEE Systems Conference, April 9-12, 2007, pp. 333-338, (with C.M. Lawler and S.A. Szygenda).
• Disaster Tolerant Systems Engineering for Critical Infrastructure Protection, IEEE Systems Conference, April 9-12, 2007, pp. 2-8, (with M.A. Harper and S.A. Szygenda).
• Performance Evaluation of a Novel Table Lookup Method and Architecture for Integer Functions, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 99-104, September 11-13, 2006, (with L. Li, A. Fit-Florea, and D.W. Matula).
• A Decision Diagram Package for Reversible and Quantum Circuit Simulation, IEEE Congress on Evolutionary Computation, IEEE World Congress on Computational Intelligence (WCCI), July 16-21, 2006, pp. 8597-8604 on Proceedings CD-ROM, (best paper of session, with D.M. Miller and D. Goodman).
• QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 17-20, 2006, pp. 30-30 on Proceedings CD-ROM, (with D.M. Miller).
• A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 17-20, 2006, pp. 33-33 on Proceedings CD-ROM, (electronic version only, with L. Li and M. Perkowski).
• A Digit Serial Algorithm for the Integer Power Operation, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 30-May 2, 2006, pp. 302-307, (with L. Li and D.W. Matula).
• BDD-Based Conjunctive Decomposition Using a Genetic Algorithm and Dependent Variable Affinity, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 277-280, (with L. Li and S. Szygenda).
• Early Evaluation for Phased Logic Circuits Using BDDs and MVL, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 400-403, (with K. Fazel and R.B. Reese).
• A Survey and Comparison of Digital Logic Simulators, IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), August 7-10, 2005, p. 156 (abstract), full paper on Proceedings CD-ROM, (with M. Gunes, F. Kocan, and S.A. Szygenda).
• Disaster Tolerant Computing and Communications, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 14-17, 2005, pp. 171-173, (invited paper, with S. Szygenda).
• IT Application Downtime, Executive Visibility and Disaster Tolerant Computing, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 14-17, 2005, pp. 165-170, (invited paper, with M. A. Harper and C. Lawler).
• Combining Simulation and Formal Verification for Integrated Circuit Design Validation, 9^th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 10-13, 2005, pp. 92-97, (with L. Li and S. Szygenda).
• Lookup Table Structures for Multiplicative Inverses Modulo 2^k, IEEE Symposium on Computer Arithmetic (ARITH), June 27-29, 2005, pp. 130-135, (D.W. Matula and A. Fit-Florea).
• The Karhunen-Loève Transform of Discrete MVL Functions, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 18-21, 2005, pp. 194-199.
• Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k, IEEE Symposium on VLSI (ISVLSI), May 10-11, 2005, pp. 130-135, (with L. Li, A. Fit-Florea, and D.W. Matula).
• A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams, International Conference on Information Technology (ITCC), April 4-6, 2005, pp. 432-435, (with F.P. Coyle).
• From UML to HDL: a Model Driven Architectural Approach to Hardware-Software Co-Design, Information Systems: New Generations Conference (ISNG), April 4-6, 2005, pp. 88-93, (with F.P. Coyle).
• Static Variable Ordering in ZBDDs for Path Delay Fault Coverage Calculation, IEEE Mid-west Symposium on Circuits and Systems (MWSCAS), July 25-28, 2004, pp. I-509 - I-512, (with F. Kocan and M. Gunes).
• Test Vector Generation and Classification Using FSM Traversals, IEEE International Symposium on Circuits and Systems (ISCAS), May 23-26, 2004, pp. V-309 - V-312, (with R. Marczynski and S. Szygenda).
• Performance Enhancement in Phased Logic Circuits Using Automatic Slack Matching Buffer Insertion, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 26-28, 2004, pp. 413-416, (K. Fazel, L. Li, R. B. Reese and C. Traver).
• A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), February 19-20, 2004, pp. 32-36, (with L. Li and S. Szygenda).
• Spectral Transforms of Mixed-radix MVL Functions, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 16-19, 2003, pp. 329-333.
• A Coarse-Grain Phased Logic CPU, IEEE International Symposium on Asynchronous Circuits & Systems (ASYNC), May 12-16, 2003, pp. 2-13, (with R. Reese and C. Traver).
• PLFire: A Visualization Tool for Asynchronous Phased Logic Designs, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 3-7, 2003, pp. 1096-1097, (poster presentation, with K. Fazel and R. B. Reese).
• A Fine-grain Phased Logic CPU, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), February 20-21, 2003, pp. 70-79, (with R. B. Reese and C. Traver).
• Switching Activity Estimation of FSMs for Low Power Synthesis, IEEE International Symposium on Circuits and Systems (ISCAS), May 26-29, 2002, vol. IV, pp. 65-68, (with M. Kerttu, P. Lindgren and R. Drechsler).
• Chrestenson Spectrum Computation Using Cayley Color Graphs, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 15-18, 2002, pp. 123-128, (with D. M. Miller).
• Efficient Adder Circuits Based on a Conservative Reversible Logic Gate, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 25-26, 2002, pp. 83-88, (with J. W. Bruce, L. Shivakumaraiah, P. S. Kokate and X. Li).
• Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations, Great Lakes Symposium on VLSI (GLSVLSI), April 18-19, 2002, pp. 178-183, (with W. Townsend, D. M. Miller and R. Drechsler).
• Multi-output Timed Shannon Circuits, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 47-52, April 25-26, 2002, (with R. Drechsler and D. Michael Miller).
• Generalized Early Evaluation in Self-timed Circuits, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 255-259, March 4-8, 2002, (with K. Fazel, R. Reese and C. Traver).
• Fast and Efficient Equivalence Checking based on NAND-BDDs, IFIP International Conference on Very Large Scale Integration (VLSI-SOC), pp. 401-405, December 3-5, 2001, (with R. Drechsler).
• Cell Designs for Self-timed FPGAs, IEEE ASIC/SOC Conference (ASIC), pp.175-179, September 2001, (with C. Traver and R. Reese).
• Arithmetic Logic Circuits using Self-Timed Bit-Level Dataflow and Early Evaluation, IEEE International Conference on Computer Design (ICCD), pp. 18-23, September 23-26, 2001, ( with R. Reese and C. Traver).
• Application of a Hardware Synthesis Technique for Database Query Optimization, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 26-28, 2001, pp. 715-718, (with V. Komaragiri and R. Drechsler).
• Evolutionary Algorithm Approach for Symbolic FSM Traversals, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 26-28, 2001, pp. 506-509, (with R. Drechsler).
• Spectral Decision Diagrams Using Graph Transformations, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 13-16, 2001, pp. 713-717, (with R. Drechsler).
• Low Power Optimization Technique for BDD Mapped Circuits, IEEE/IEICE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), January 30-February 2, 2001, pp. 615-621, (P. Lindgren, M. Kerrtu and R. Drechsler).
• Cache Resident Data Locality Analysis, ACM/IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), August 29-September 1, 2000, pp.539-546, (with Q. G. Samdani).
• MDD-based Synthesis of Multi-Valued Logic Networks, IEEE International Symposium for Multiple-Valued Logic (ISMVL), May 23-25, 2000, pp. 41-46, (with R. Drechsler and D. Wessels).
• Computation of Spectral Information from Logic Netlists, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 23-25, 2000,  pp. 53-58, (with  R. Drechsler).
• A Method for Approximate Equivalence Checking, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 23-25, 2000, pp. 447-452, (with R. Drechsler and W. Günther).
• Extracting spectral information from AND/OR representations, IEEE Electrotechnical and Computer Science Conference (ERK), September 23-25, 1999, pp. 27-32, ( with R. Drechsler and A. Žužek).
• SBDD Variable Reordering Based on Probabilistic and Evolutionary Algorithms, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 22-24, 1999, pp. 381-387, (with J. P. Williams, R. Drechsler, N. Drechsler and D. Wessels).
• Tradeoff Analysis of Integer Multiplier Circuits Implemented in FPGAs, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 22-24, 1999, pp. 301-304, (with J. Gaiche and J. Lemieux).
• Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), presentation poster, March 9-12, 1999, pp. 758-759, (with J. P. Williams, R. Drechsler and N. Drechsler).
• Modified Haar Transform Calculation Using Digital Circuit Output Probabilities, IEEE International Conference on Information, Communications & Signal Processing (ICICS), September 9-12, 1997, pp. 52 - 58, (invited paper).
• Applications of Circuit Probability Computation Using Decision Diagrams, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 20 - 22, 1997, pp. 683-687, (with R. P. Moore and J. C. Cordova).
• A Technique for Multiprocessor Memory Resource Estimation, World Multiconference on Systematics, Cybernetics and Informatics, July 7-11, 1997, Volume 1, pp. 212-218, (with J. D. Bullard and D. L. Andrews).
• Graph Analysis and Transformation Techniques for Run-Time Minimization in a Multi-Threaded Architecture, 30-th Hawaii International Conference on Systems Sciences (HICSS), January 1997, Volume 1, pp. 566-575, (with D. L. Andrews).
• Behavioral to Structural Translation in ESOP Form Using the Verilog HDL, IEEE International Verilog HDL Conference (IVL), March 1994, pp. 58-62, (best paper award with V. S. S. Nair)
• Combinational Logic Synthesis Using Spectral Techniques, IEEE/ACM European Design Automation Conference (EURO-DAC), September 1993, pp. 358-363, (with V. S. S. Nair).

NATIONAL/INTERNATIONAL WORKSHOPS

• Toffoli Gate Cascade Generation Using ESOP Minimization and QMDD-based Swapping, Proceedings of the Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 23-24, 2009, pp. 63-72, (with J. Rice, K. Fazel, K. Kent).
• QMDD and Spectral Transformation of Binary and Multiple-Valued Functions, 8th International Workshop on Boolean Problems (IWBP), September 18-19, 2008, pp. 137-144, (with D.M. Miller).
• System-on-Chip Power Consumption Refinement and Analysis, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, November 15-16, 2007, pp. 81-84, (with D. Feinstein and F. Kocan).
• Quantum Logic Circuit Simulation Based on the QMDD Data Structure, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 99-105, (with D. Goodman, D.Y. Feinstein, and D.M. Miller).
• ESOP Transformation to Majority Gates for Quantum-dot Cellular Automata Logic Synthesis, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 43-50, (with D.Y. Feinstein).
• Components of Disaster Tolerant Computing, International Workshop on Information Assurance, in conjunction with the IEEE International Performance Computing and Communications Conference, April 11-13, 2007, pp. 380-386, (with C.M. Lawler and M.A. Harper).
• Boolean Function Matching Using Walsh Spectral Decision Diagrams, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, October 29-30, 2006, pp. 127-130, (with J. Moore, K. Fazel and D. M. Miller).
• Discrete Function KL Spectrum Computation over Symmetry Groups of Arbitrary Size, Proceedings of the International Symposium on Representations and Methodology of Future Computing Technologies (formerly, Reed-Muller Workshop, RMW05), September 5-6, 2005, pp. 110-113, (with Lun Li).
• A Standard Cell Implementation of a Phased Logic CPU, Workshop on Token Based Computing, Proceedings of the Workshop on Token Based Computing (ToBaCo), June 22, 2004, pp. 49-58, (with R. Reese and C. Traver).
• Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation, International Workshop on System-on-Chip for Real Time Applications (SOCRT), July 6-7, 2002, pp. 400-409, (with R. Drechsler, M. Kerttu and P. Lindgren).
• Low Power Optimization Technique for BDD Mapped Finite State Machines, International Workshop on Logic and Synthesis (IWLS), June 4-7, 2002, pp. 143-148, (with M. Kerttu, P. Lindgren and R. Drechsler).
• Transformations Amongst the Walsh, Haar, Arithmetic and Reed-Muller Spectral Domains, International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), August 10-11,  2001, pp. 215-225, (with D. M. Miller and R. Drechsler).
• Arithmetic Logic Circuits using Self-Timed Bit-Level Dataflow and Early Evaluation, International Workshop on Logic and Synthesis (IWLS), June 12-15,  2001, pp. 72-77, (with R. Reese and C. Traver).
• Low Power Optimization Technique for BDD Mapped Circuits, International Workshop on Logic Synthesis (IWLS), May 31-June 2, 2000, pp. 221-230, (with P. Lindgren and M. Kerttu).
• Probabilistic Equivalence Checking Using Partial Haar Spectral Diagrams, International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), August 1999, pp. 123-132, (with R. Drechsler and W. Günther).
• Logic Synthesis Based on the Structure of an Ordered DD, International Workshop on Logic Synthesis (IWLS), July 1999, pp. 21-25, (with D. M. Wessels).
• Integration of CAD Tools and Structured Design Principles in an Undergraduate Computer Engineering Curriculum, Workshop on Computer Architecture Education, International Symposium on Computer Architecture (ISCA), June 1998, (with D. L. Andrews).
• Multiprocessor Resource Estimation Using a Stochastic Modeling Approach,  Symposium on Parallel and Distributed Processing, Workshop on Resource Estimation (SPDP), October 1996, (with D. L. Andrews and J. D. Bullard).
• Fast Reed-Muller Spectrum Computation Using Output Probabilities, Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), August 1995, pp. 281 - 287, (with V. S. S. Nair).
• Parity Function Detection and Realization Using a Small Set of Spectral Coefficients, IEEE/ACM International Workshop on Logic Synthesis (IWLS), May 1995, pp. 8-39 - 8-47, (with V. S. S. Nair).
• A Numerical Method for Reed-Muller Circuit Synthesis, Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), September 1993, pp. 69-74, (with V. S. S. Nair).

REGIONAL CONFERENCES

• Teaching a Laboratory Intensive Class in a Distance Education Mode, ASEE 2008 Midwest Section Conference, September 18-19, 2008, (with J. Moore and R.W. Skeith).
• Perl for Introductory Programming Classes, ASEE 2007 Midwest Section Conference, September 19-21, 2007, (with J. Moore and R.W. Skeith).
• Prefix Parallel Adder Virtual Implementation in Reversible Logic, IEEE Region 5 Technical Conference, April 20-22, 2007, pp. 74-80, (with D.Y. Feinstein and V.S.S. Nair).
• Multilevel Variable Length Shifter Design for an Iterated Shift-and-Add Product Operation , IEEE Region 5 Technical Conference, April 20-22, 2007, pp. 234-238, (with J. Moore and D.W. Matula).
• Encouraging Computer Engineering Students to Take the Fundamentals of Engineering (FE) Examination, ASEE 2006 Midwest Section Conference, September 15, 2006, on Proceedings CD-ROM, (with J. Moore and R. W. Skeith).
• An Undergraduate Course in Perl: An All Purpose Programming Language, ASEE Midwest Section Conference, September 14-16, 2005, on Proceedings CD-ROM, (with J. Moore and R.W. Skeith).
• A Modular and Specifications Oriented Digital Circuit Design Laboratory, ASEE Midwest Section Conference, September 29-October 1, 2004, (with J. Moore and R. W. Skeith).
• Research Results in Equivalence Checking, NSF Design, Service and Manufacturing Grantees and Research Conference, January 5-8, 2004, (with A. Mukherjee).
• UNIX Scripting and High-level Language Education Using an Emulator, ASEE Midwest Section Conference, September 2002, (with R. W. Skeith).
• Learning and Using UNIX on a MS Windows© Based Computer, Memphis Area Engineering and Sciences Conference (MAESC), May 10, 2002, p. 36, (with R. W. Skeith).
• Computation of Disjoint Cube Representations Using a Maximal Binate Variable Heuristic, IEEE Southeastern Symposium on System Theory, March 18-19, 2002, pp. 417-421, (with L. Shivakumaraiah).
• Odd/Even Cube Covering for Minimizing ESOP Circuits, IEEE Southeastern Symposium on System Theory, March 2000, pp. 274-278, (with B. Q. Vu and R. Drechsler).
• Performance Evaluation of a Data Driven Architecture, 1996 Arkansas Computer Conference, March 1996, pp. 71-76.

ARTICLES AND OPINION PIECES

• Smart Meters can be Hacked: Security Experts, Dallas-Fort Worth KXAS, Channel 5, NBC affiliate, local news interview aired on Sept. 20 and 21, 2009, (anchored by Ken Kalthoff with interviews of M.A. Thornton and V.S. Nair), video.
• Software Engineering PE Examination Development Approved, IEEE-USA Today's Engineer, September 2009.
• Why Computer Engineering Students Should Take the Fundamentals of Engineering Examination and How Professors can Help, IEEE-USA Today's Engineer, June 2009, (with J. Moore and R. W. Skeith).
• Is It Time to License Software Engineers?, PE The Magazine for Professional Engineers, published by the NSPE, December 2007, p. 26-29, (authored by D. Boykin, with quotes from interview of M. A. Thornton)
• Criteria 2000 - The New Game - How Does it Play Out, ChAPTER One Online Magazine, Student magazine of the AIChE, September 1998, vol. 1, no. 1, (with R. E. Babcock and R. W. Skeith).

ABSTRACTS

• Advances in Quantum Computing Fault Tolerance and Testing, IEEE High Assurance Systems Engineering Symposium (HASE), November 14-16, 2007, pp. 369-370, (with D. Y. Feinstein and V.S.S. Nair).
• A Second Undergraduate Course in Digital Logic Design: The Datapath+Controller-based Approach, ASEE 2003 Southeastern Section Conference, April 2003, (with A. S. Collins).
• UNIX and High-level Language Education Using Windows Operating Systems, ASEE 2001 Southeastern Section Meeting, April 2001, (with R. W. Skeith).
• Binary Decision Diagram Visualization: A Research Experience for Undergraduates, ASEE Thirty-Fourth Midwest Section Conference, April 1999, (with R. W. Skeith, S. M. Karp, J. N. Taylor).
• Integration of CAD Tools and Structured Design Principles in an Undergraduate CE Curriculum, IEEE Computer Architecture Technical Committee Newsletter, February 1999, pp.8-9, (with D. L. Andrews).
• Assessment Analysis in Criteria 2000, ASEE Thirty-Third Midwest Section Conference, April 1998, (with R. W. Skeith).
• Integration of Hardware Description Languages into an Undergraduate Design Laboratory Course, ASEE Thirty-First Midwest Section Conference, April 1996.

TECHNICAL REPORTS

• An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal for a New MCM Routing Algorithm, Technical Report, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, 1996, (written by C. N. Frisbee, directed by M. A. Thornton).
• Iterative Combinational Logic Synthesis Techniques Using Spectral Data, Technical Report, Southern Methodist University, CSE-9208, 1992 (with V. S. S. Nair).
• Applications and Efficient Computation of Spectral Coefficients for Digital Logic, Technical Report, Southern Methodist University, CSE-9413, 1994, (with V. S. S. Nair).
• Boolean Function Spectrum Computation Using a Structural Representation, Technical Report, Southern Methodist University, CSE-9440, 1994, (with V. S. S. Nair).
• Reed-Muller Circuit Synthesis Using Numerical Methods, Technical Report, Southern Methodist University, CSE-9319, 1993, (with V. S. S. Nair).

DISERTATIONS/THESIS

• Computer-Aided-Design Methods for Emerging Quantum Computing Techniques, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, April 18, 2008, (written by David Feinstein, directed by M.A. Thornton).
• Quantum Logic Implementation of Unary Arithmetic Operations with Inheritance, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 24, 2008, (written by Laura Spenner, directed by M.A. Thornton).
• Hardware Acceleration of Software Library String Functions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 2007, (written by P. Kulkarni, directed by M.A. Thornton).
• An Automated Tool for HDL and Configuration File Generation from UML System Descriptions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, June 2007, (written by K. Hawkins, directed by M.A. Thornton).
• A Quantum Logic Simulator Based on Decision Diagrams, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2007, (written by D. Goodman, directed by M.A. Thornton).
• Integrated Techniques for the Formal Verification and Validation of Digital Systems, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, May 2006, (written by Lun Li, directed by M. A. Thornton)
• Crosstalk Delay Analysis in Very Deep Submicron VLSI Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004, (written by Satyendra Datla, directed by M. A. Thornton).
• Performance Enhancement Techniques for Phased Logic Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004, (written by Kenneth B. Fazel, directed by M. A. Thornton).
• Application of Decision Diagrams for Information Storage and Retrieval, M.S.E.E. thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, May 2002, (written by Vivek Komarigiri, directed by M. A. Thornton).
• ESOP Circuit Minimization Based on the Function On-Set, M.S.E.E. thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, August 2000, (written by Likai Chai, directed by M. A. Thornton).
• A Split Data Cache Organization Based on Run-time Data Locality Estimation, Ph.D. dissertation, Dept. of Computer Science and Computer Engineering, University of Arkansas, May 2000, (written by Quazi Galib Samdani, directed by M. A. Thornton).
• An FPGA Approach for SNR Estimation Using Phase-Only Data, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, August 1999, (written by Pramodini Arramreddy, directed by M. A. Thornton).
• A BDD Variable Reordering Heuristic Based on Output Probability Periodicity, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, December 1998, (written by Joshua P. Williams, directed by M. A. Thornton).
• Probability Based Variable Ordering and Reordering Heuristics for Decision Diagrams, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, August 1997, (written by Roger P. Moore, directed by M. A. Thornton).
• Implementation of Compiler, Viewer, and Parallelism Analysis Software for the IF1 Language, M. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, December 1996, (written by Suwanto, directed by M. A. Thornton).
• Spectral Based Numerical Methods for Combinational Logic Synthesis, Ph.D. dissertation, Department of Computer Science and Engineering, Southern Methodist University, August 4, 1995.